| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreMachineFunctionInfo.cpp | 38 const TargetRegisterClass &RC = XCore::GRRegsRegClass;
43 LRSpillSlot = MFI.CreateFixedObject(TRI.getSpillSize(RC), 0, true);
45 LRSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC),
46 TRI.getSpillAlign(RC), true);
56 const TargetRegisterClass &RC = XCore::GRRegsRegClass;
60 MFI.CreateStackObject(TRI.getSpillSize(RC), TRI.getSpillAlign(RC), true);
69 const TargetRegisterClass &RC = XCore::GRRegsRegClass;
72 unsigned Size = TRI.getSpillSize(RC);
73 Align Alignment = TRI.getSpillAlign(RC);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| RegisterBank.cpp | 35 const TargetRegisterClass &RC = *TRI.getRegClass(RCId);
37 if (!covers(RC))
43 // RegisterBankInfo to find the subclasses of RC, to make sure
48 if (!RC.hasSubClassEq(&SubRC))
61 bool RegisterBank::covers(const TargetRegisterClass &RC) const {
63 return ContainedRegClasses.test(RC.getID());
105 const TargetRegisterClass &RC = *TRI->getRegClass(RCId);
107 if (covers(RC))
108 OS << LS << TRI->getRegClassName(&RC);
|
| InstructionSelect.cpp | 251 const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg);
252 if (!RC) {
259 if (Ty.isValid() && Ty.getSizeInBits() > TRI.getRegSizeInBits(*RC)) {
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| LiveStacks.cpp | 57 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) {
66 S2RCMap.insert(std::make_pair(Slot, RC));
70 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC);
82 const TargetRegisterClass *RC = getIntervalRegClass(Slot);
83 if (RC)
84 OS << " [" << TRI->getRegClassName(RC) << "]\n";
|
| RegAllocBase.cpp | 127 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg->reg());
128 ArrayRef<MCPhysReg> AllocOrder = RegClassInfo.getOrder(RC);
|
| AggressiveAntiDepBreaker.h | 48 const TargetRegisterClass *RC;
|
| MIRVRegNamerUtils.cpp | 169 const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg);
170 return RC ? MRI.createVirtualRegister(RC, LowerName)
|
| RegisterClassInfo.cpp | 89 /// compute - Compute the preferred allocation order for RC with reserved
92 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
93 assert(RC && "no register class given");
94 RCInfo &RCI = RegClass[RC->getID()];
98 unsigned NumRegs = RC->getNumRegs();
111 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
148 // Check if RC is a proper sub-class.
150 TRI->getLargestLegalSuperClass(RC, *MF))
151 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
158 dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = ["
[all...] |
| SwiftErrorValueTracking.cpp | 36 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
37 auto VReg = MF->getRegInfo().createVirtualRegister(RC);
58 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
59 Register VReg = MF->getRegInfo().createVirtualRegister(RC);
126 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
133 Register VReg = MF->getRegInfo().createVirtualRegister(RC);
241 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
243 UpwardsUse ? UUseVReg : MF->getRegInfo().createVirtualRegister(RC);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| GCNRegPressure.cpp | 75 const auto RC = MRI.getRegClass(Reg);
77 return STI->isSGPRClass(RC) ?
78 (STI->getRegSizeInBits(*RC) == 32 ? SGPR32 : SGPR_TUPLE) :
79 STI->hasAGPRs(RC) ?
80 (STI->getRegSizeInBits(*RC) == 32 ? AGPR32 : AGPR_TUPLE) :
81 (STI->getRegSizeInBits(*RC) == 32 ? VGPR32 : VGPR_TUPLE);
|
| SIPreAllocateWWMRegs.cpp | 159 const TargetRegisterClass *RC = TRI->getPhysRegClass(PhysReg);
160 FI = FrameInfo.CreateSpillStackObject(TRI->getSpillSize(*RC),
161 TRI->getSpillAlign(*RC));
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyReplacePhysRegs.cpp | 86 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(PReg);
92 VReg = MRI.createVirtualRegister(RC);
|
| WebAssemblyInstrInfo.cpp | 63 const TargetRegisterClass *RC =
69 if (RC == &WebAssembly::I32RegClass)
71 else if (RC == &WebAssembly::I64RegClass)
73 else if (RC == &WebAssembly::F32RegClass)
75 else if (RC == &WebAssembly::F64RegClass)
77 else if (RC == &WebAssembly::V128RegClass)
79 else if (RC == &WebAssembly::FUNCREFRegClass)
81 else if (RC == &WebAssembly::EXTERNREFRegClass)
|
| WebAssemblyRegColoring.cpp | 140 const TargetRegisterClass *RC = MRI->getRegClass(Old);
145 if (MRI->getRegClass(SortedIntervals[C]->reg()) != RC)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86FixupSetCC.cpp | 101 const TargetRegisterClass *RC = MF.getSubtarget<X86Subtarget>().is64Bit()
104 if (!MRI->constrainRegClass(ZExt->getOperand(0).getReg(), RC)) {
114 Register ZeroReg = MRI->createVirtualRegister(RC);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64DeadRegisterDefinitionsPass.cpp | 160 const TargetRegisterClass *RC = TII->getRegClass(Desc, I, TRI, MF);
162 if (RC == nullptr) {
165 } else if (RC->contains(AArch64::WZR))
167 else if (RC->contains(AArch64::XZR))
|
| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| FastISelEmitter.cpp | 36 const CodeGenRegisterClass *RC;
41 InstructionMemo(StringRef Name, const CodeGenRegisterClass *RC,
44 : Name(Name), RC(RC), SubRegNo(std::move(SubRegNo)),
264 const CodeGenRegisterClass *RC = nullptr;
268 RC = &Target.getRegisterClass(OpLeafRec);
270 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec);
272 RC = OrigDstRC;
277 if (!RC)
283 if (DstRC != RC && !DstRC->hasSubClass(RC)
[all...] |
| /src/common/lib/libc/hash/sha3/ |
| keccak.c | 153 * RC[i] = \sum_{j = 0,...,6} rc(j + 7i) 2^(2^j - 1),
154 * rc(t) = (x^t mod x^8 + x^6 + x^5 + x^4 + 1) mod x in GF(2)[x]
156 static const uint64_t RC[24] = {
186 A[0] ^= RC[i];
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRAsmPrinter.cpp | 114 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
115 unsigned BytesPerReg = TRI.getRegSizeInBits(*RC) / 8;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| BitTracker.cpp | 49 // RegisterCell RC = BT.get(Reg);
50 // if (RC[3].is(1))
115 raw_ostream &operator<<(raw_ostream &OS, const BT::RegisterCell &RC) {
116 unsigned n = RC.Bits.size();
126 for (unsigned i = 1, n = RC.Bits.size(); i < n; ++i) {
127 const BT::BitValue &V = RC[i];
128 const BT::BitValue &SV = RC[Start];
165 OS << "]:" << RC[Start];
168 const BT::BitValue &SV = RC[Start];
201 bool BT::RegisterCell::meet(const RegisterCell &RC, Register SelfR)
[all...] |
| HexagonBitTracker.cpp | 92 const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
93 unsigned ID = RC.getID();
96 bool IsSubLo = (Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo));
108 << TRI.getRegClassName(&RC) << '\n';
117 for (auto &RC : {HvxVRRegClass, HvxWRRegClass, HvxQRRegClass,
119 if (RC.contains(Reg))
120 return TRI.getRegSizeInBits(RC);
123 if (const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg))
124 return TRI.getRegSizeInBits(*RC);
131 const TargetRegisterClass &RC, unsigned Idx) const
250 #define rc macro
975 #undef rc macro
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsMachineFunction.cpp | 71 const TargetRegisterClass *RC;
74 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
76 Register V0 = RegInfo.createVirtualRegister(RC);
77 Register V1 = RegInfo.createVirtualRegister(RC);
152 const TargetRegisterClass &RC =
158 TRI.getSpillSize(RC), TRI.getSpillAlign(RC), false);
167 const TargetRegisterClass &RC = Mips::GPR32RegClass;
172 TRI.getSpillSize(RC), TRI.getSpillAlign(RC), false)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 136 const TargetRegisterClass *RC = nullptr;
138 RC = TRI->getAllocatableClass(
142 UseRC = RC;
143 else if (RC) {
145 TRI->getCommonSubClass(UseRC, RC);
211 const TargetRegisterClass *RC =
220 (Node->isDivergent() || (RC && TRI->isDivergentRegClass(RC))));
221 if (RC)
222 VTRC = TRI->getCommonSubClass(RC, VTRC)
[all...] |
| ScheduleDAGSDNodes.cpp | 133 const TargetRegisterClass *RC =
135 Cost = RC->getCopyCost();
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kRegisterInfo.cpp | 76 const TargetRegisterClass *RC) const {
78 if (RC->contains(*Super))
93 const TargetRegisterClass *RC = *I;
94 if ((VT == MVT::Other || isTypeLegalForClass(*RC, VT)) &&
95 RC->contains(reg) &&
97 (BestRC->hasSubClass(RC) && RC->getNumRegs() > BestRC->getNumRegs())))
98 BestRC = RC;
|
