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    Searched defs:RD (Results 1 - 25 of 115) sorted by relevancy

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  /src/external/apache2/llvm/dist/clang/lib/AST/
VTTBuilder.cpp 60 const CXXRecordDecl *RD = Base.getBase();
62 for (const auto &I : RD->bases()) {
70 const ASTRecordLayout &Layout = Ctx.getASTRecordLayout(RD);
85 const CXXRecordDecl *RD = Base.getBase();
89 if (!RD->getNumVBases() && !BaseIsMorallyVirtual)
92 for (const auto &I : RD->bases()) {
117 const ASTRecordLayout &Layout = Ctx.getASTRecordLayout(RD);
154 void VTTBuilder::LayoutVirtualVTTs(const CXXRecordDecl *RD,
156 for (const auto &I : RD->bases()) {
180 const CXXRecordDecl *RD = Base.getBase()
    [all...]
DeclCXX.cpp 179 const CXXRecordDecl *RD = WorkList.pop_back_val();
180 for (const CXXBaseSpecifier &BaseSpec : RD->bases()) {
601 auto Visit = [&](const CXXRecordDecl *RD) -> bool {
602 RD = RD->getCanonicalDecl();
610 if (!RD->data().HasBasesWithFields) {
616 if (RD == Base)
624 if (Bases.count(RD))
629 if (M.insert(RD).second)
630 WorkList.push_back(RD);
    [all...]
ComputeDependence.cpp 591 CXXRecordDecl *RD = dyn_cast_or_null<CXXRecordDecl>(DC);
592 if (RD && RD->isDependentContext() && RD->isCurrentInstantiation(DC)) {
MicrosoftCXXABI.cpp 115 bool isNearlyEmpty(const CXXRecordDecl *RD) const override {
120 getCopyConstructorForExceptionObject(CXXRecordDecl *RD) override {
121 return RecordToCopyCtor[RD];
125 addCopyConstructorForExceptionObject(CXXRecordDecl *RD,
128 assert(RecordToCopyCtor[RD] == nullptr || RecordToCopyCtor[RD] == CD);
129 RecordToCopyCtor[RD] = CD;
174 static bool usesMultipleInheritanceModel(const CXXRecordDecl *RD) {
175 while (RD->getNumBases() > 0) {
176 if (RD->getNumBases() > 1
    [all...]
NestedNameSpecifier.cpp 135 CXXRecordDecl *RD) {
139 Mockup.Specifier = RD;
219 CXXRecordDecl *RD = static_cast<CXXRecordDecl *>(Specifier);
220 for (const auto &Base : RD->bases())
619 CXXRecordDecl *RD,
622 Representation = NestedNameSpecifier::SuperSpecifier(Context, RD);
  /src/external/apache2/llvm/dist/clang/lib/Sema/
SemaFixItUtils.cpp 208 const CXXRecordDecl *RD = T->getAsCXXRecordDecl();
209 if (!RD || !RD->hasDefinition())
211 if (LangOpts.CPlusPlus11 && !RD->hasUserProvidedDefaultConstructor())
213 if (RD->isAggregate())
SemaCXXScopeSpec.cpp 281 CXXRecordDecl *RD = nullptr;
285 RD = MD->getParent();
289 RD = cast<CXXRecordDecl>(S->getEntity());
294 if (!RD) {
297 } else if (RD->isLambda()) {
300 } else if (RD->getNumBases() == 0) {
301 Diag(SuperLoc, diag::err_no_base_classes) << RD->getName();
305 SS.MakeSuper(Context, RD, SuperLoc, ColonColonLoc);
  /src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Checkers/
CastSizeChecker.cpp 56 const RecordDecl *RD = RT->getDecl();
57 RecordDecl::field_iterator Iter(RD->field_begin());
58 RecordDecl::field_iterator End(RD->field_end());
73 } else if (RD->hasFlexibleArrayMember()) {
LLVMConventionsChecker.cpp 65 static bool IsClangType(const RecordDecl *RD) {
66 return RD->getName() == "Type" && InNamespace(RD, "clang");
69 static bool IsClangDecl(const RecordDecl *RD) {
70 return RD->getName() == "Decl" && InNamespace(RD, "clang");
73 static bool IsClangStmt(const RecordDecl *RD) {
74 return RD->getName() == "Stmt" && InNamespace(RD, "clang");
77 static bool IsClangAttr(const RecordDecl *RD) {
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/MCA/Stages/
InOrderIssueStage.cpp 101 const ReadDescriptor &RD = RS.getDescriptor();
102 const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID);
108 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID);
131 assert(STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID) < 0);
133 -STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID));
  /src/external/apache2/llvm/dist/llvm/lib/Target/VE/MCTargetDesc/
VEInstPrinter.cpp 225 int RD = (int)MI->getOperand(OpNum).getImm();
226 O << VERDToString((VERD::RoundingMode)RD);
  /src/external/bsd/less/dist/lesstest/
pipeline.c 7 #define RD 0
29 if (verbose) fprintf(stderr, "less child: in %d, out %d, close %d,%d\n", less_in_pipe[RD], screen_in_pipe[WR], less_in_pipe[WR], screen_in_pipe[RD]);
31 close(screen_in_pipe[RD]);
32 dup_std(less_in_pipe[RD], screen_in_pipe[WR]);
52 if (verbose) fprintf(stderr, "screen child: in %d, out %d, close %d\n", screen_in_pipe[RD], screen_out_pipe[WR], screen_out_pipe[RD]);
53 close(screen_out_pipe[RD]);
54 dup_std(screen_in_pipe[RD], screen_out_pipe[WR]);
87 pipeline->less_in_pipe[RD] = pipeline->less_in_pipe[WR] = -1
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  /src/external/apache2/llvm/dist/clang/lib/CodeGen/
CGCXX.cpp 250 const CXXRecordDecl *RD) {
254 llvm::Value *VTable = CGM.getCXXABI().getAddrOfVTable(RD, CharUnits());
259 const VTableLayout &VTLayout = CGM.getItaniumVTableContext().getVTableLayout(RD);
261 VTLayout.getAddressPoint(BaseSubobject(RD, CharUnits::Zero()));
286 const auto *RD = cast<CXXRecordDecl>(RT->getDecl());
289 return BuildAppleKextVirtualDestructorCall(DD, Dtor_Complete, RD);
291 return ::BuildAppleKextVirtualCall(*this, MD, Ty, RD);
300 const CXXRecordDecl *RD) {
306 return ::BuildAppleKextVirtualCall(*this, GlobalDecl(DD, Type), Ty, RD);
CodeGenTBAA.cpp 101 const RecordDecl *RD = TTy->getDecl()->getDefinition();
103 if (!RD)
105 if (RD->hasFlexibleArrayMember())
107 // RD can be struct, union, class, interface or enum.
109 if (RD->isStruct() || RD->isClass())
284 const RecordDecl *RD = TTy->getDecl()->getDefinition();
285 if (RD->hasFlexibleArrayMember())
289 if (const CXXRecordDecl *Decl = dyn_cast<CXXRecordDecl>(RD))
293 const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
    [all...]
CGCXXABI.cpp 50 const auto *RD =
53 CGM.getTypes().arrangeCXXMethodType(RD, FPT, /*FD=*/nullptr));
256 const CXXRecordDecl *RD) {
293 std::vector<CharUnits> CGCXXABI::getVBPtrOffsets(const CXXRecordDecl *RD) {
ObjectFilePCHContainerOperations.cpp 227 if (const RecordDecl *RD = dyn_cast<RecordDecl>(D))
228 Builder->getModuleDebugInfo()->completeRequiredType(RD);
CodeGenTypes.cpp 48 void CodeGenTypes::addRecordTypeName(const RecordDecl *RD,
53 OS << RD->getKindName() << '.';
58 PrintingPolicy Policy = RD->getASTContext().getPrintingPolicy();
63 if (RD->getIdentifier()) {
66 if (RD->getDeclContext())
67 RD->printQualifiedName(OS, Policy);
69 RD->printName(OS);
70 } else if (const TypedefNameDecl *TDD = RD->getTypedefNameForAnonDecl()) {
128 isSafeToConvert(const RecordDecl *RD, CodeGenTypes &CGT,
132 if (!AlreadyChecked.insert(RD).second
    [all...]
  /src/sys/arch/sparc/sparc/
db_disasm.c 102 #define RD(x) (((x) & 0x1f) << 25)
164 d -- destination register operand stored in rd
167 e -- floating destination register in rd
194 G -- privileged register encoded in rd
195 H -- state register encoded in rd
313 {(FORMAT3(2, 0x30, 1) | RD(0xf)), "sir", "i"},
407 {FORMAT3(2, OP3_X(2,8), 0), "rd", "Bd"},
409 {FORMAT3(2, OP3_X(2,8), 0), "rd", "Yd"},
421 {FORMAT3(2, OP3_X(2,9), 0), "rd", "Pd"},
433 {FORMAT3(2, OP3_X(2,10), 0), "rd", "Wd"}
    [all...]
  /src/sys/arch/sparc64/sparc64/
db_disasm.c 107 #define RD(x) (((x) & 0x1f) << 25)
169 d -- destination register operand stored in rd
172 e -- floating destination register in rd
199 G -- privileged register encoded in rd
200 H -- state register encoded in rd
318 {(FORMAT3(2, 0x30, 1) | RD(0xf)), "sir", "i"},
412 {FORMAT3(2, OP3_X(2,8), 0), "rd", "Bd"},
414 {FORMAT3(2, OP3_X(2,8), 0), "rd", "Yd"},
426 {FORMAT3(2, OP3_X(2,9), 0), "rd", "Pd"},
438 {FORMAT3(2, OP3_X(2,10), 0), "rd", "Wd"}
    [all...]
  /src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Core/
Store.cpp 238 const CXXRecordDecl *RD = TVR->getValueType()->getAsCXXRecordDecl();
239 if (!RD)
246 return Expected->getCanonicalDecl() == RD->getCanonicalDecl();
  /src/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/
RegisterFile.cpp 478 const ReadDescriptor &RD = RS.getDescriptor();
480 const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID);
496 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID);
511 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID);
558 const ReadDescriptor &RD = RS.getDescriptor();
560 const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID);
564 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID);
571 assert(STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID) < 0);
573 -STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID));
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonGenPredicate.cpp 217 RegisterSubReg RD = MI->getOperand(0);
218 if (RD.R.isVirtual())
219 PredGPRs.insert(RD);
  /src/external/gpl3/gdb.old/dist/sim/microblaze/
microblaze.h 29 #define RD CPU.regs[rd]
  /src/external/gpl3/gdb/dist/sim/microblaze/
microblaze.h 29 #define RD CPU.regs[rd]
  /src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Checkers/UninitializedObject/
UninitializedObjectChecker.cpp 120 /// Checks whether RD contains a field with a name or type name that matches
122 static bool shouldIgnoreRecord(const RecordDecl *RD, StringRef Pattern);
282 const RecordDecl *RD = R->getValueType()->getAsRecordDecl()->getDefinition();
284 if (!RD) {
290 shouldIgnoreRecord(RD, Opts.IgnoredRecordsWithFieldPattern)) {
298 for (const FieldDecl *I : RD->fields()) {
352 const auto *CXXRD = dyn_cast<CXXRecordDecl>(RD);
502 static bool shouldIgnoreRecord(const RecordDecl *RD, StringRef Pattern) {
505 for (const FieldDecl *FD : RD->fields()) {

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