1 /* $NetBSD: ispreg.h,v 1.35 2022/05/03 20:52:32 andvar Exp $ */ 2 /* 3 * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration 4 * All rights reserved. 5 * 6 * Additional Copyright (C) 2000-2007 by Matthew Jacob 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /* 32 * Machine Independent (well, as best as possible) register 33 * definitions for Qlogic ISP SCSI adapters. 34 */ 35 #ifndef _ISPREG_H 36 #define _ISPREG_H 37 38 /* 39 * Hardware definitions for the Qlogic ISP registers. 40 */ 41 42 /* 43 * This defines types of access to various registers. 44 * 45 * R: Read Only 46 * W: Write Only 47 * RW: Read/Write 48 * 49 * R*, W*, RW*: Read Only, Write Only, Read/Write, but only 50 * if RISC processor in ISP is paused. 51 */ 52 53 /* 54 * Offsets for various register blocks. 55 * 56 * Sad but true, different architectures have different offsets. 57 * 58 * Don't be alarmed if none of this makes sense. The original register 59 * layout set some defines in a certain pattern. Everything else has been 60 * grafted on since. For example, the ISP1080 manual will state that DMA 61 * registers start at 0x80 from the base of the register address space. 62 * That's true, but for our purposes, we define DMA_REGS_OFF for the 1080 63 * to start at offset 0x60 because the DMA registers are all defined to 64 * be DMA_BLOCK+0x20 and so on. Clear? 65 */ 66 67 #define BIU_REGS_OFF 0x00 68 69 #define PCI_MBOX_REGS_OFF 0x70 70 #define PCI_MBOX_REGS2100_OFF 0x10 71 #define PCI_MBOX_REGS2300_OFF 0x40 72 #define PCI_MBOX_REGS2400_OFF 0x80 73 #define SBUS_MBOX_REGS_OFF 0x80 74 75 #define PCI_SXP_REGS_OFF 0x80 76 #define SBUS_SXP_REGS_OFF 0x200 77 78 #define PCI_RISC_REGS_OFF 0x80 79 #define SBUS_RISC_REGS_OFF 0x400 80 81 /* Bless me! Chip designers have putzed it again! */ 82 #define ISP1080_DMA_REGS_OFF 0x60 83 #define DMA_REGS_OFF 0x00 /* same as BIU block */ 84 85 #define SBUS_REGSIZE 0x450 86 #define PCI_REGSIZE 0x100 87 88 /* 89 * NB: The *_BLOCK definitions have no specific hardware meaning. 90 * They serve simply to note to the MD layer which block of 91 * registers offsets are being accessed. 92 */ 93 #define _NREG_BLKS 5 94 #define _BLK_REG_SHFT 13 95 #define _BLK_REG_MASK (7 << _BLK_REG_SHFT) 96 #define BIU_BLOCK (0 << _BLK_REG_SHFT) 97 #define MBOX_BLOCK (1 << _BLK_REG_SHFT) 98 #define SXP_BLOCK (2 << _BLK_REG_SHFT) 99 #define RISC_BLOCK (3 << _BLK_REG_SHFT) 100 #define DMA_BLOCK (4 << _BLK_REG_SHFT) 101 102 /* 103 * Bus Interface Block Register Offsets 104 */ 105 106 #define BIU_ID_LO (BIU_BLOCK+0x0) /* R : Bus ID, Low */ 107 #define BIU2100_FLASH_ADDR (BIU_BLOCK+0x0) 108 #define BIU_ID_HI (BIU_BLOCK+0x2) /* R : Bus ID, High */ 109 #define BIU2100_FLASH_DATA (BIU_BLOCK+0x2) 110 #define BIU_CONF0 (BIU_BLOCK+0x4) /* R : Bus Configuration #0 */ 111 #define BIU_CONF1 (BIU_BLOCK+0x6) /* R : Bus Configuration #1 */ 112 #define BIU2100_CSR (BIU_BLOCK+0x6) 113 #define BIU_ICR (BIU_BLOCK+0x8) /* RW : Bus Interface Ctrl */ 114 #define BIU_ISR (BIU_BLOCK+0xA) /* R : Bus Interface Status */ 115 #define BIU_SEMA (BIU_BLOCK+0xC) /* RW : Bus Semaphore */ 116 #define BIU_NVRAM (BIU_BLOCK+0xE) /* RW : Bus NVRAM */ 117 /* 118 * These are specific to the 2300. 119 */ 120 #define BIU_REQINP (BIU_BLOCK+0x10) /* Request Queue In */ 121 #define BIU_REQOUTP (BIU_BLOCK+0x12) /* Request Queue Out */ 122 #define BIU_RSPINP (BIU_BLOCK+0x14) /* Response Queue In */ 123 #define BIU_RSPOUTP (BIU_BLOCK+0x16) /* Response Queue Out */ 124 125 #define BIU_R2HSTSLO (BIU_BLOCK+0x18) 126 #define BIU_R2HSTSHI (BIU_BLOCK+0x1A) 127 128 #define BIU_R2HST_INTR (1 << 15) /* RISC to Host Interrupt */ 129 #define BIU_R2HST_PAUSED (1 << 8) /* RISC paused */ 130 #define BIU_R2HST_ISTAT_MASK 0x3f /* intr information && status */ 131 #define ISPR2HST_ROM_MBX_OK 0x1 /* ROM mailbox cmd done ok */ 132 #define ISPR2HST_ROM_MBX_FAIL 0x2 /* ROM mailbox cmd done fail */ 133 #define ISPR2HST_MBX_OK 0x10 /* mailbox cmd done ok */ 134 #define ISPR2HST_MBX_FAIL 0x11 /* mailbox cmd done fail */ 135 #define ISPR2HST_ASYNC_EVENT 0x12 /* Async Event */ 136 #define ISPR2HST_RSPQ_UPDATE 0x13 /* Response Queue Update */ 137 #define ISPR2HST_RQST_UPDATE 0x14 /* Resquest Queue Update */ 138 #define ISPR2HST_RIO_16 0x15 /* RIO 1-16 */ 139 #define ISPR2HST_FPOST 0x16 /* Low 16 bits fast post */ 140 #define ISPR2HST_FPOST_CTIO 0x17 /* Low 16 bits fast post ctio */ 141 142 /* fifo command stuff- mostly for SPI */ 143 #define DFIFO_COMMAND (BIU_BLOCK+0x60) /* RW : Command FIFO Port */ 144 #define RDMA2100_CONTROL DFIFO_COMMAND 145 #define DFIFO_DATA (BIU_BLOCK+0x62) /* RW : Data FIFO Port */ 146 147 /* 148 * Putzed DMA register layouts. 149 */ 150 #define CDMA_CONF (DMA_BLOCK+0x20) /* RW*: DMA Configuration */ 151 #define CDMA2100_CONTROL CDMA_CONF 152 #define CDMA_CONTROL (DMA_BLOCK+0x22) /* RW*: DMA Control */ 153 #define CDMA_STATUS (DMA_BLOCK+0x24) /* R : DMA Status */ 154 #define CDMA_FIFO_STS (DMA_BLOCK+0x26) /* R : DMA FIFO Status */ 155 #define CDMA_COUNT (DMA_BLOCK+0x28) /* RW*: DMA Transfer Count */ 156 #define CDMA_ADDR0 (DMA_BLOCK+0x2C) /* RW*: DMA Address, Word 0 */ 157 #define CDMA_ADDR1 (DMA_BLOCK+0x2E) /* RW*: DMA Address, Word 1 */ 158 #define CDMA_ADDR2 (DMA_BLOCK+0x30) /* RW*: DMA Address, Word 2 */ 159 #define CDMA_ADDR3 (DMA_BLOCK+0x32) /* RW*: DMA Address, Word 3 */ 160 161 #define DDMA_CONF (DMA_BLOCK+0x40) /* RW*: DMA Configuration */ 162 #define TDMA2100_CONTROL DDMA_CONF 163 #define DDMA_CONTROL (DMA_BLOCK+0x42) /* RW*: DMA Control */ 164 #define DDMA_STATUS (DMA_BLOCK+0x44) /* R : DMA Status */ 165 #define DDMA_FIFO_STS (DMA_BLOCK+0x46) /* R : DMA FIFO Status */ 166 #define DDMA_COUNT_LO (DMA_BLOCK+0x48) /* RW*: DMA Xfer Count, Low */ 167 #define DDMA_COUNT_HI (DMA_BLOCK+0x4A) /* RW*: DMA Xfer Count, High */ 168 #define DDMA_ADDR0 (DMA_BLOCK+0x4C) /* RW*: DMA Address, Word 0 */ 169 #define DDMA_ADDR1 (DMA_BLOCK+0x4E) /* RW*: DMA Address, Word 1 */ 170 /* these are for the 1040A cards */ 171 #define DDMA_ADDR2 (DMA_BLOCK+0x50) /* RW*: DMA Address, Word 2 */ 172 #define DDMA_ADDR3 (DMA_BLOCK+0x52) /* RW*: DMA Address, Word 3 */ 173 174 175 /* 176 * Bus Interface Block Register Definitions 177 */ 178 /* BUS CONFIGURATION REGISTER #0 */ 179 #define BIU_CONF0_HW_MASK 0x000F /* Hardware revision mask */ 180 /* BUS CONFIGURATION REGISTER #1 */ 181 182 #define BIU_SBUS_CONF1_PARITY 0x0100 /* Enable parity checking */ 183 #define BIU_SBUS_CONF1_FCODE_MASK 0x00F0 /* Fcode cycle mask */ 184 185 #define BIU_PCI_CONF1_FIFO_128 0x0040 /* 128 bytes FIFO threshold */ 186 #define BIU_PCI_CONF1_FIFO_64 0x0030 /* 64 bytes FIFO threshold */ 187 #define BIU_PCI_CONF1_FIFO_32 0x0020 /* 32 bytes FIFO threshold */ 188 #define BIU_PCI_CONF1_FIFO_16 0x0010 /* 16 bytes FIFO threshold */ 189 #define BIU_BURST_ENABLE 0x0004 /* Global enable Bus bursts */ 190 #define BIU_SBUS_CONF1_FIFO_64 0x0003 /* 64 bytes FIFO threshold */ 191 #define BIU_SBUS_CONF1_FIFO_32 0x0002 /* 32 bytes FIFO threshold */ 192 #define BIU_SBUS_CONF1_FIFO_16 0x0001 /* 16 bytes FIFO threshold */ 193 #define BIU_SBUS_CONF1_FIFO_8 0x0000 /* 8 bytes FIFO threshold */ 194 #define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */ 195 #define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */ 196 197 #define BIU_PCI1080_CONF1_SXP0 0x0100 /* SXP bank #1 select */ 198 #define BIU_PCI1080_CONF1_SXP1 0x0200 /* SXP bank #2 select */ 199 #define BIU_PCI1080_CONF1_DMA 0x0300 /* DMA bank select */ 200 201 /* ISP2100 Bus Control/Status Register */ 202 203 #define BIU2100_ICSR_REGBSEL 0x30 /* RW: register bank select */ 204 #define BIU2100_RISC_REGS (0 << 4) /* RISC Regs */ 205 #define BIU2100_FB_REGS (1 << 4) /* FrameBuffer Regs */ 206 #define BIU2100_FPM0_REGS (2 << 4) /* FPM 0 Regs */ 207 #define BIU2100_FPM1_REGS (3 << 4) /* FPM 1 Regs */ 208 #define BIU2100_NVRAM_OFFSET (1 << 14) 209 #define BIU2100_FLASH_UPPER_64K 0x04 /* RW: Upper 64K Bank Select */ 210 #define BIU2100_FLASH_ENABLE 0x02 /* RW: Enable Flash RAM */ 211 #define BIU2100_SOFT_RESET 0x01 212 /* SOFT RESET FOR ISP2100 is same bit, but in this register, not ICR */ 213 214 215 /* BUS CONTROL REGISTER */ 216 #define BIU_ICR_ENABLE_DMA_INT 0x0020 /* Enable DMA interrupts */ 217 #define BIU_ICR_ENABLE_CDMA_INT 0x0010 /* Enable CDMA interrupts */ 218 #define BIU_ICR_ENABLE_SXP_INT 0x0008 /* Enable SXP interrupts */ 219 #define BIU_ICR_ENABLE_RISC_INT 0x0004 /* Enable Risc interrupts */ 220 #define BIU_ICR_ENABLE_ALL_INTS 0x0002 /* Global enable all inter */ 221 #define BIU_ICR_SOFT_RESET 0x0001 /* Soft Reset of ISP */ 222 223 #define BIU_IMASK (BIU_ICR_ENABLE_RISC_INT|BIU_ICR_ENABLE_ALL_INTS) 224 225 #define BIU2100_ICR_ENABLE_ALL_INTS 0x8000 226 #define BIU2100_ICR_ENA_FPM_INT 0x0020 227 #define BIU2100_ICR_ENA_FB_INT 0x0010 228 #define BIU2100_ICR_ENA_RISC_INT 0x0008 229 #define BIU2100_ICR_ENA_CDMA_INT 0x0004 230 #define BIU2100_ICR_ENABLE_RXDMA_INT 0x0002 231 #define BIU2100_ICR_ENABLE_TXDMA_INT 0x0001 232 #define BIU2100_ICR_DISABLE_ALL_INTS 0x0000 233 234 #define BIU2100_IMASK (BIU2100_ICR_ENA_RISC_INT|BIU2100_ICR_ENABLE_ALL_INTS) 235 236 /* BUS STATUS REGISTER */ 237 #define BIU_ISR_DMA_INT 0x0020 /* DMA interrupt pending */ 238 #define BIU_ISR_CDMA_INT 0x0010 /* CDMA interrupt pending */ 239 #define BIU_ISR_SXP_INT 0x0008 /* SXP interrupt pending */ 240 #define BIU_ISR_RISC_INT 0x0004 /* Risc interrupt pending */ 241 #define BIU_ISR_IPEND 0x0002 /* Global interrupt pending */ 242 243 #define BIU2100_ISR_INT_PENDING 0x8000 /* Global interrupt pending */ 244 #define BIU2100_ISR_FPM_INT 0x0020 /* FPM interrupt pending */ 245 #define BIU2100_ISR_FB_INT 0x0010 /* FB interrupt pending */ 246 #define BIU2100_ISR_RISC_INT 0x0008 /* Risc interrupt pending */ 247 #define BIU2100_ISR_CDMA_INT 0x0004 /* CDMA interrupt pending */ 248 #define BIU2100_ISR_RXDMA_INT_PENDING 0x0002 /* Global interrupt pending */ 249 #define BIU2100_ISR_TXDMA_INT_PENDING 0x0001 /* Global interrupt pending */ 250 251 #define INT_PENDING(isp, isr) \ 252 IS_FC(isp)? \ 253 (IS_24XX(isp)? (isr & BIU2400_ISR_RISC_INT) : (isr & BIU2100_ISR_RISC_INT)) :\ 254 (isr & BIU_ISR_RISC_INT) 255 256 #define INT_PENDING_MASK(isp) \ 257 (IS_FC(isp)? (IS_24XX(isp)? BIU2400_ISR_RISC_INT : BIU2100_ISR_RISC_INT) : \ 258 (BIU_ISR_RISC_INT)) 259 260 /* BUS SEMAPHORE REGISTER */ 261 #define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */ 262 #define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */ 263 264 /* NVRAM SEMAPHORE REGISTER */ 265 #define BIU_NVRAM_CLOCK 0x0001 266 #define BIU_NVRAM_SELECT 0x0002 267 #define BIU_NVRAM_DATAOUT 0x0004 268 #define BIU_NVRAM_DATAIN 0x0008 269 #define BIU_NVRAM_BUSY 0x0080 /* 2322/24xx only */ 270 #define ISP_NVRAM_READ 6 271 272 /* COMNMAND && DATA DMA CONFIGURATION REGISTER */ 273 #define DMA_ENABLE_SXP_DMA 0x0008 /* Enable SXP to DMA Data */ 274 #define DMA_ENABLE_INTS 0x0004 /* Enable interrupts to RISC */ 275 #define DMA_ENABLE_BURST 0x0002 /* Enable Bus burst trans */ 276 #define DMA_DMA_DIRECTION 0x0001 /* 277 * Set DMA direction: 278 * 0 - DMA FIFO to host 279 * 1 - Host to DMA FIFO 280 */ 281 282 /* COMMAND && DATA DMA CONTROL REGISTER */ 283 #define DMA_CNTRL_SUSPEND_CHAN 0x0010 /* Suspend DMA transfer */ 284 #define DMA_CNTRL_CLEAR_CHAN 0x0008 /* 285 * Clear FIFO and DMA Channel, 286 * reset DMA registers 287 */ 288 #define DMA_CNTRL_CLEAR_FIFO 0x0004 /* Clear DMA FIFO */ 289 #define DMA_CNTRL_RESET_INT 0x0002 /* Clear DMA interrupt */ 290 #define DMA_CNTRL_STROBE 0x0001 /* Start DMA transfer */ 291 292 /* 293 * Variants of same for 2100 294 */ 295 #define DMA_CNTRL2100_CLEAR_CHAN 0x0004 296 #define DMA_CNTRL2100_RESET_INT 0x0002 297 298 299 300 /* DMA STATUS REGISTER */ 301 #define DMA_SBUS_STATUS_PIPE_MASK 0x00C0 /* DMA Pipeline status mask */ 302 #define DMA_SBUS_STATUS_CHAN_MASK 0x0030 /* Channel status mask */ 303 #define DMA_SBUS_STATUS_BUS_PARITY 0x0008 /* Parity Error on bus */ 304 #define DMA_SBUS_STATUS_BUS_ERR 0x0004 /* Error Detected on bus */ 305 #define DMA_SBUS_STATUS_TERM_COUNT 0x0002 /* DMA Transfer Completed */ 306 #define DMA_SBUS_STATUS_INTERRUPT 0x0001 /* Enable DMA channel inter */ 307 308 #define DMA_PCI_STATUS_INTERRUPT 0x8000 /* Enable DMA channel inter */ 309 #define DMA_PCI_STATUS_RETRY_STAT 0x4000 /* Retry status */ 310 #define DMA_PCI_STATUS_CHAN_MASK 0x3000 /* Channel status mask */ 311 #define DMA_PCI_STATUS_FIFO_OVR 0x0100 /* DMA FIFO overrun cond */ 312 #define DMA_PCI_STATUS_FIFO_UDR 0x0080 /* DMA FIFO underrun cond */ 313 #define DMA_PCI_STATUS_BUS_ERR 0x0040 /* Error Detected on bus */ 314 #define DMA_PCI_STATUS_BUS_PARITY 0x0020 /* Parity Error on bus */ 315 #define DMA_PCI_STATUS_CLR_PEND 0x0010 /* DMA clear pending */ 316 #define DMA_PCI_STATUS_TERM_COUNT 0x0008 /* DMA Transfer Completed */ 317 #define DMA_PCI_STATUS_DMA_SUSP 0x0004 /* DMA suspended */ 318 #define DMA_PCI_STATUS_PIPE_MASK 0x0003 /* DMA Pipeline status mask */ 319 320 /* DMA Status Register, pipeline status bits */ 321 #define DMA_SBUS_PIPE_FULL 0x00C0 /* Both pipeline stages full */ 322 #define DMA_SBUS_PIPE_OVERRUN 0x0080 /* Pipeline overrun */ 323 #define DMA_SBUS_PIPE_STAGE1 0x0040 /* 324 * Pipeline stage 1 Loaded, 325 * stage 2 empty 326 */ 327 #define DMA_PCI_PIPE_FULL 0x0003 /* Both pipeline stages full */ 328 #define DMA_PCI_PIPE_OVERRUN 0x0002 /* Pipeline overrun */ 329 #define DMA_PCI_PIPE_STAGE1 0x0001 /* 330 * Pipeline stage 1 Loaded, 331 * stage 2 empty 332 */ 333 #define DMA_PIPE_EMPTY 0x0000 /* All pipeline stages empty */ 334 335 /* DMA Status Register, channel status bits */ 336 #define DMA_SBUS_CHAN_SUSPEND 0x0030 /* Channel error or suspended */ 337 #define DMA_SBUS_CHAN_TRANSFER 0x0020 /* Chan transfer in progress */ 338 #define DMA_SBUS_CHAN_ACTIVE 0x0010 /* Chan trans to host active */ 339 #define DMA_PCI_CHAN_TRANSFER 0x3000 /* Chan transfer in progress */ 340 #define DMA_PCI_CHAN_SUSPEND 0x2000 /* Channel error or suspended */ 341 #define DMA_PCI_CHAN_ACTIVE 0x1000 /* Chan trans to host active */ 342 #define ISP_DMA_CHAN_IDLE 0x0000 /* Chan idle (normal comp) */ 343 344 345 /* DMA FIFO STATUS REGISTER */ 346 #define DMA_FIFO_STATUS_OVERRUN 0x0200 /* FIFO Overrun Condition */ 347 #define DMA_FIFO_STATUS_UNDERRUN 0x0100 /* FIFO Underrun Condition */ 348 #define DMA_FIFO_SBUS_COUNT_MASK 0x007F /* FIFO Byte count mask */ 349 #define DMA_FIFO_PCI_COUNT_MASK 0x00FF /* FIFO Byte count mask */ 350 351 /* 352 * 2400 Interface Offsets and Register Definitions 353 * 354 * The 2400 looks quite different in terms of registers from other QLogic cards. 355 * It is getting to be a genuine pain and challenge to keep the same model 356 * for all. 357 */ 358 #define BIU2400_FLASH_ADDR (BIU_BLOCK+0x00) 359 #define BIU2400_FLASH_DATA (BIU_BLOCK+0x04) 360 #define BIU2400_CSR (BIU_BLOCK+0x08) 361 #define BIU2400_ICR (BIU_BLOCK+0x0C) 362 #define BIU2400_ISR (BIU_BLOCK+0x10) 363 364 #define BIU2400_REQINP (BIU_BLOCK+0x1C) /* Request Queue In */ 365 #define BIU2400_REQOUTP (BIU_BLOCK+0x20) /* Request Queue Out */ 366 #define BIU2400_RSPINP (BIU_BLOCK+0x24) /* Response Queue In */ 367 #define BIU2400_RSPOUTP (BIU_BLOCK+0x28) /* Response Queue Out */ 368 369 #define BIU2400_PRI_REQINP (BIU_BLOCK+0x2C) /* Priority Request Q In */ 370 #define BIU2400_PRI_REQOUTP (BIU_BLOCK+0x30) /* Priority Request Q Out */ 371 372 #define BIU2400_ATIO_RSPINP (BIU_BLOCK+0x3C) /* ATIO Queue In */ 373 #define BIU2400_ATIO_RSPOUTP (BIU_BLOCK+0x40) /* ATIO Queue Out */ 374 375 #define BIU2400_R2HSTSLO (BIU_BLOCK+0x44) 376 #define BIU2400_R2HSTSHI (BIU_BLOCK+0x46) 377 378 #define BIU2400_HCCR (BIU_BLOCK+0x48) 379 #define BIU2400_GPIOD (BIU_BLOCK+0x4C) 380 #define BIU2400_GPIOE (BIU_BLOCK+0x50) 381 #define BIU2400_HSEMA (BIU_BLOCK+0x58) 382 383 /* BIU2400_FLASH_ADDR definitions */ 384 #define BIU2400_FLASH_DFLAG (1 << 30) 385 386 /* BIU2400_CSR definitions */ 387 #define BIU2400_NVERR (1 << 18) 388 #define BIU2400_DMA_ACTIVE (1 << 17) /* RO */ 389 #define BIU2400_DMA_STOP (1 << 16) 390 #define BIU2400_FUNCTION (1 << 15) /* RO */ 391 #define BIU2400_PCIX_MODE(x) (((x) >> 8) & 0xf) /* RO */ 392 #define BIU2400_CSR_64BIT (1 << 2) /* RO */ 393 #define BIU2400_FLASH_ENABLE (1 << 1) 394 #define BIU2400_SOFT_RESET (1 << 0) 395 396 /* BIU2400_ICR definitions */ 397 #define BIU2400_ICR_ENA_RISC_INT 0x8 398 #define BIU2400_IMASK (BIU2400_ICR_ENA_RISC_INT) 399 400 /* BIU2400_ISR definitions */ 401 #define BIU2400_ISR_RISC_INT 0x8 402 403 #define BIU2400_R2HST_INTR BIU_R2HST_INTR 404 #define BIU2400_R2HST_PAUSED BIU_R2HST_PAUSED 405 #define BIU2400_R2HST_ISTAT_MASK 0x1f 406 /* interrupt status meanings */ 407 #define ISP2400R2HST_ROM_MBX_OK 0x1 /* ROM mailbox cmd done ok */ 408 #define ISP2400R2HST_ROM_MBX_FAIL 0x2 /* ROM mailbox cmd done fail */ 409 #define ISP2400R2HST_MBX_OK 0x10 /* mailbox cmd done ok */ 410 #define ISP2400R2HST_MBX_FAIL 0x11 /* mailbox cmd done fail */ 411 #define ISP2400R2HST_ASYNC_EVENT 0x12 /* Async Event */ 412 #define ISP2400R2HST_RSPQ_UPDATE 0x13 /* Response Queue Update */ 413 #define ISP2400R2HST_ATIO_RSPQ_UPDATE 0x1C /* ATIO Response Queue Update */ 414 #define ISP2400R2HST_ATIO_RQST_UPDATE 0x1D /* ATIO Request Queue Update */ 415 416 /* BIU2400_HCCR definitions */ 417 418 #define HCCR_2400_CMD_NOP 0x00000000 419 #define HCCR_2400_CMD_RESET 0x10000000 420 #define HCCR_2400_CMD_CLEAR_RESET 0x20000000 421 #define HCCR_2400_CMD_PAUSE 0x30000000 422 #define HCCR_2400_CMD_RELEASE 0x40000000 423 #define HCCR_2400_CMD_SET_HOST_INT 0x50000000 424 #define HCCR_2400_CMD_CLEAR_HOST_INT 0x60000000 425 #define HCCR_2400_CMD_CLEAR_RISC_INT 0xA0000000 426 427 #define HCCR_2400_RISC_ERR(x) (((x) >> 12) & 0x7) /* RO */ 428 #define HCCR_2400_RISC2HOST_INT (1 << 6) /* RO */ 429 #define HCCR_2400_RISC_RESET (1 << 5) /* RO */ 430 431 432 /* 433 * Mailbox Block Register Offsets 434 */ 435 436 #define INMAILBOX0 (MBOX_BLOCK+0x0) 437 #define INMAILBOX1 (MBOX_BLOCK+0x2) 438 #define INMAILBOX2 (MBOX_BLOCK+0x4) 439 #define INMAILBOX3 (MBOX_BLOCK+0x6) 440 #define INMAILBOX4 (MBOX_BLOCK+0x8) 441 #define INMAILBOX5 (MBOX_BLOCK+0xA) 442 #define INMAILBOX6 (MBOX_BLOCK+0xC) 443 #define INMAILBOX7 (MBOX_BLOCK+0xE) 444 445 #define OUTMAILBOX0 (MBOX_BLOCK+0x0) 446 #define OUTMAILBOX1 (MBOX_BLOCK+0x2) 447 #define OUTMAILBOX2 (MBOX_BLOCK+0x4) 448 #define OUTMAILBOX3 (MBOX_BLOCK+0x6) 449 #define OUTMAILBOX4 (MBOX_BLOCK+0x8) 450 #define OUTMAILBOX5 (MBOX_BLOCK+0xA) 451 #define OUTMAILBOX6 (MBOX_BLOCK+0xC) 452 #define OUTMAILBOX7 (MBOX_BLOCK+0xE) 453 454 /* 455 * Strictly speaking, it's 456 * SCSI && 2100 : 8 MBOX registers 457 * 2200: 24 MBOX registers 458 * 2300/2400: 32 MBOX registers 459 */ 460 #define MBOX_OFF(n) (MBOX_BLOCK + ((n) << 1)) 461 #define NMBOX(isp) \ 462 (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ 463 ((isp)->isp_type & ISP_HA_FC))? 12 : 6) 464 #define NMBOX_BMASK(isp) \ 465 (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ 466 ((isp)->isp_type & ISP_HA_FC))? 0xfff : 0x3f) 467 468 #define MAX_MAILBOX(isp) ((IS_FC(isp))? 12 : 8) 469 #define MAILBOX_STORAGE 12 470 /* if timeout == 0, then default timeout is picked */ 471 #define MBCMD_DEFAULT_TIMEOUT 100000 /* 100 ms */ 472 typedef struct { 473 uint16_t param[MAILBOX_STORAGE]; 474 uint16_t ibits; 475 uint16_t obits; 476 uint32_t 477 lineno : 16, 478 : 12, 479 logval : 4; 480 uint32_t timeout; 481 const char *func; 482 } mbreg_t; 483 #define MBSINIT(mbxp, code, loglev, timo) \ 484 ISP_MEMZERO((mbxp), sizeof (mbreg_t)); \ 485 (mbxp)->param[0] = code; \ 486 (mbxp)->lineno = __LINE__; \ 487 (mbxp)->func = __func__; \ 488 (mbxp)->logval = loglev; \ 489 (mbxp)->timeout = timo 490 491 492 /* 493 * Fibre Protocol Module and Frame Buffer Register Offsets/Definitions (2X00). 494 * NB: The RISC processor must be paused and the appropriate register 495 * bank selected via BIU2100_CSR bits. 496 */ 497 498 #define FPM_DIAG_CONFIG (BIU_BLOCK + 0x96) 499 #define FPM_SOFT_RESET 0x0100 500 501 #define FBM_CMD (BIU_BLOCK + 0xB8) 502 #define FBMCMD_FIFO_RESET_ALL 0xA000 503 504 505 /* 506 * SXP Block Register Offsets 507 */ 508 #define SXP_PART_ID (SXP_BLOCK+0x0) /* R : Part ID Code */ 509 #define SXP_CONFIG1 (SXP_BLOCK+0x2) /* RW*: Configuration Reg #1 */ 510 #define SXP_CONFIG2 (SXP_BLOCK+0x4) /* RW*: Configuration Reg #2 */ 511 #define SXP_CONFIG3 (SXP_BLOCK+0x6) /* RW*: Configuration Reg #2 */ 512 #define SXP_INSTRUCTION (SXP_BLOCK+0xC) /* RW*: Instruction Pointer */ 513 #define SXP_RETURN_ADDR (SXP_BLOCK+0x10) /* RW*: Return Address */ 514 #define SXP_COMMAND (SXP_BLOCK+0x14) /* RW*: Command */ 515 #define SXP_INTERRUPT (SXP_BLOCK+0x18) /* R : Interrupt */ 516 #define SXP_SEQUENCE (SXP_BLOCK+0x1C) /* RW*: Sequence */ 517 #define SXP_GROSS_ERR (SXP_BLOCK+0x1E) /* R : Gross Error */ 518 #define SXP_EXCEPTION (SXP_BLOCK+0x20) /* RW*: Exception Enable */ 519 #define SXP_OVERRIDE (SXP_BLOCK+0x24) /* RW*: Override */ 520 #define SXP_LIT_BASE (SXP_BLOCK+0x28) /* RW*: Literal Base */ 521 #define SXP_USER_FLAGS (SXP_BLOCK+0x2C) /* RW*: User Flags */ 522 #define SXP_USER_EXCEPT (SXP_BLOCK+0x30) /* RW*: User Exception */ 523 #define SXP_BREAKPOINT (SXP_BLOCK+0x34) /* RW*: Breakpoint */ 524 #define SXP_SCSI_ID (SXP_BLOCK+0x40) /* RW*: SCSI ID */ 525 #define SXP_DEV_CONFIG1 (SXP_BLOCK+0x42) /* RW*: Device Config Reg #1 */ 526 #define SXP_DEV_CONFIG2 (SXP_BLOCK+0x44) /* RW*: Device Config Reg #2 */ 527 #define SXP_PHASE_PTR (SXP_BLOCK+0x48) /* RW*: SCSI Phase Pointer */ 528 #define SXP_BUF_PTR (SXP_BLOCK+0x4C) /* RW*: SCSI Buffer Pointer */ 529 #define SXP_BUF_CTR (SXP_BLOCK+0x50) /* RW*: SCSI Buffer Counter */ 530 #define SXP_BUFFER (SXP_BLOCK+0x52) /* RW*: SCSI Buffer */ 531 #define SXP_BUF_BYTE (SXP_BLOCK+0x54) /* RW*: SCSI Buffer Byte */ 532 #define SXP_BUF_WD (SXP_BLOCK+0x56) /* RW*: SCSI Buffer Word */ 533 #define SXP_BUF_WD_TRAN (SXP_BLOCK+0x58) /* RW*: SCSI Buffer Wd xlate */ 534 #define SXP_FIFO (SXP_BLOCK+0x5A) /* RW*: SCSI FIFO */ 535 #define SXP_FIFO_STATUS (SXP_BLOCK+0x5C) /* RW*: SCSI FIFO Status */ 536 #define SXP_FIFO_TOP (SXP_BLOCK+0x5E) /* RW*: SCSI FIFO Top Resid */ 537 #define SXP_FIFO_BOTTOM (SXP_BLOCK+0x60) /* RW*: SCSI FIFO Bot Resid */ 538 #define SXP_TRAN_REG (SXP_BLOCK+0x64) /* RW*: SCSI Transfer Reg */ 539 #define SXP_TRAN_CNT_LO (SXP_BLOCK+0x68) /* RW*: SCSI Trans Count */ 540 #define SXP_TRAN_CNT_HI (SXP_BLOCK+0x6A) /* RW*: SCSI Trans Count */ 541 #define SXP_TRAN_CTR_LO (SXP_BLOCK+0x6C) /* RW*: SCSI Trans Counter */ 542 #define SXP_TRAN_CTR_HI (SXP_BLOCK+0x6E) /* RW*: SCSI Trans Counter */ 543 #define SXP_ARB_DATA (SXP_BLOCK+0x70) /* R : SCSI Arb Data */ 544 #define SXP_PINS_CTRL (SXP_BLOCK+0x72) /* RW*: SCSI Control Pins */ 545 #define SXP_PINS_DATA (SXP_BLOCK+0x74) /* RW*: SCSI Data Pins */ 546 #define SXP_PINS_DIFF (SXP_BLOCK+0x76) /* RW*: SCSI Diff Pins */ 547 548 /* for 1080/1280/1240 only */ 549 #define SXP_BANK1_SELECT 0x100 550 551 552 /* SXP CONF1 REGISTER */ 553 #define SXP_CONF1_ASYNCH_SETUP 0xF000 /* Asynchronous setup time */ 554 #define SXP_CONF1_SELECTION_UNIT 0x0000 /* Selection time unit */ 555 #define SXP_CONF1_SELECTION_TIMEOUT 0x0600 /* Selection timeout */ 556 #define SXP_CONF1_CLOCK_FACTOR 0x00E0 /* Clock factor */ 557 #define SXP_CONF1_SCSI_ID 0x000F /* SCSI id */ 558 559 /* SXP CONF2 REGISTER */ 560 #define SXP_CONF2_DISABLE_FILTER 0x0040 /* Disable SCSI rec filters */ 561 #define SXP_CONF2_REQ_ACK_PULLUPS 0x0020 /* Enable req/ack pullups */ 562 #define SXP_CONF2_DATA_PULLUPS 0x0010 /* Enable data pullups */ 563 #define SXP_CONF2_CONFIG_AUTOLOAD 0x0008 /* Enable dev conf auto-load */ 564 #define SXP_CONF2_RESELECT 0x0002 /* Enable reselection */ 565 #define SXP_CONF2_SELECT 0x0001 /* Enable selection */ 566 567 /* SXP INTERRUPT REGISTER */ 568 #define SXP_INT_PARITY_ERR 0x8000 /* Parity error detected */ 569 #define SXP_INT_GROSS_ERR 0x4000 /* Gross error detected */ 570 #define SXP_INT_FUNCTION_ABORT 0x2000 /* Last cmd aborted */ 571 #define SXP_INT_CONDITION_FAILED 0x1000 /* Last cond failed test */ 572 #define SXP_INT_FIFO_EMPTY 0x0800 /* SCSI FIFO is empty */ 573 #define SXP_INT_BUF_COUNTER_ZERO 0x0400 /* SCSI buf count == zero */ 574 #define SXP_INT_XFER_ZERO 0x0200 /* SCSI trans count == zero */ 575 #define SXP_INT_INT_PENDING 0x0080 /* SXP interrupt pending */ 576 #define SXP_INT_CMD_RUNNING 0x0040 /* SXP is running a command */ 577 #define SXP_INT_INT_RETURN_CODE 0x000F /* Interrupt return code */ 578 579 580 /* SXP GROSS ERROR REGISTER */ 581 #define SXP_GROSS_OFFSET_RESID 0x0040 /* Req/Ack offset not zero */ 582 #define SXP_GROSS_OFFSET_UNDERFLOW 0x0020 /* Req/Ack offset underflow */ 583 #define SXP_GROSS_OFFSET_OVERFLOW 0x0010 /* Req/Ack offset overflow */ 584 #define SXP_GROSS_FIFO_UNDERFLOW 0x0008 /* SCSI FIFO underflow */ 585 #define SXP_GROSS_FIFO_OVERFLOW 0x0004 /* SCSI FIFO overflow */ 586 #define SXP_GROSS_WRITE_ERR 0x0002 /* SXP and RISC wrote to reg */ 587 #define SXP_GROSS_ILLEGAL_INST 0x0001 /* Bad inst loaded into SXP */ 588 589 /* SXP EXCEPTION REGISTER */ 590 #define SXP_EXCEPT_USER_0 0x8000 /* Enable user exception #0 */ 591 #define SXP_EXCEPT_USER_1 0x4000 /* Enable user exception #1 */ 592 #define PCI_SXP_EXCEPT_SCAM 0x0400 /* SCAM Selection enable */ 593 #define SXP_EXCEPT_BUS_FREE 0x0200 /* Enable Bus Free det */ 594 #define SXP_EXCEPT_TARGET_ATN 0x0100 /* Enable TGT mode atten det */ 595 #define SXP_EXCEPT_RESELECTED 0x0080 /* Enable ReSEL exc handling */ 596 #define SXP_EXCEPT_SELECTED 0x0040 /* Enable SEL exc handling */ 597 #define SXP_EXCEPT_ARBITRATION 0x0020 /* Enable ARB exc handling */ 598 #define SXP_EXCEPT_GROSS_ERR 0x0010 /* Enable gross error except */ 599 #define SXP_EXCEPT_BUS_RESET 0x0008 /* Enable Bus Reset except */ 600 601 /* SXP OVERRIDE REGISTER */ 602 #define SXP_ORIDE_EXT_TRIGGER 0x8000 /* Enable external trigger */ 603 #define SXP_ORIDE_STEP 0x4000 /* Enable single step mode */ 604 #define SXP_ORIDE_BREAKPOINT 0x2000 /* Enable breakpoint reg */ 605 #define SXP_ORIDE_PIN_WRITE 0x1000 /* Enable write to SCSI pins */ 606 #define SXP_ORIDE_FORCE_OUTPUTS 0x0800 /* Force SCSI outputs on */ 607 #define SXP_ORIDE_LOOPBACK 0x0400 /* Enable SCSI loopback mode */ 608 #define SXP_ORIDE_PARITY_TEST 0x0200 /* Enable parity test mode */ 609 #define SXP_ORIDE_TRISTATE_ENA_PINS 0x0100 /* Tristate SCSI enable pins */ 610 #define SXP_ORIDE_TRISTATE_PINS 0x0080 /* Tristate SCSI pins */ 611 #define SXP_ORIDE_FIFO_RESET 0x0008 /* Reset SCSI FIFO */ 612 #define SXP_ORIDE_CMD_TERMINATE 0x0004 /* Terminate cur SXP com */ 613 #define SXP_ORIDE_RESET_REG 0x0002 /* Reset SXP registers */ 614 #define SXP_ORIDE_RESET_MODULE 0x0001 /* Reset SXP module */ 615 616 /* SXP COMMANDS */ 617 #define SXP_RESET_BUS_CMD 0x300b 618 619 /* SXP SCSI ID REGISTER */ 620 #define SXP_SELECTING_ID 0x0F00 /* (Re)Selecting id */ 621 #define SXP_SELECT_ID 0x000F /* Select id */ 622 623 /* SXP DEV CONFIG1 REGISTER */ 624 #define SXP_DCONF1_SYNC_HOLD 0x7000 /* Synchronous data hold */ 625 #define SXP_DCONF1_SYNC_SETUP 0x0F00 /* Synchronous data setup */ 626 #define SXP_DCONF1_SYNC_OFFSET 0x000F /* Synchronous data offset */ 627 628 629 /* SXP DEV CONFIG2 REGISTER */ 630 #define SXP_DCONF2_FLAGS_MASK 0xF000 /* Device flags */ 631 #define SXP_DCONF2_WIDE 0x0400 /* Enable wide SCSI */ 632 #define SXP_DCONF2_PARITY 0x0200 /* Enable parity checking */ 633 #define SXP_DCONF2_BLOCK_MODE 0x0100 /* Enable blk mode xfr count */ 634 #define SXP_DCONF2_ASSERTION_MASK 0x0007 /* Assersion period mask */ 635 636 637 /* SXP PHASE POINTER REGISTER */ 638 #define SXP_PHASE_STATUS_PTR 0x1000 /* Status buffer offset */ 639 #define SXP_PHASE_MSG_IN_PTR 0x0700 /* Msg in buffer offset */ 640 #define SXP_PHASE_COM_PTR 0x00F0 /* Command buffer offset */ 641 #define SXP_PHASE_MSG_OUT_PTR 0x0007 /* Msg out buffer offset */ 642 643 644 /* SXP FIFO STATUS REGISTER */ 645 #define SXP_FIFO_TOP_RESID 0x8000 /* Top residue reg full */ 646 #define SXP_FIFO_ACK_RESID 0x4000 /* Wide transfers odd resid */ 647 #define SXP_FIFO_COUNT_MASK 0x001C /* Words in SXP FIFO */ 648 #define SXP_FIFO_BOTTOM_RESID 0x0001 /* Bottom residue reg full */ 649 650 651 /* SXP CONTROL PINS REGISTER */ 652 #define SXP_PINS_CON_PHASE 0x8000 /* Scsi phase valid */ 653 #define SXP_PINS_CON_PARITY_HI 0x0400 /* Parity pin */ 654 #define SXP_PINS_CON_PARITY_LO 0x0200 /* Parity pin */ 655 #define SXP_PINS_CON_REQ 0x0100 /* SCSI bus REQUEST */ 656 #define SXP_PINS_CON_ACK 0x0080 /* SCSI bus ACKNOWLEDGE */ 657 #define SXP_PINS_CON_RST 0x0040 /* SCSI bus RESET */ 658 #define SXP_PINS_CON_BSY 0x0020 /* SCSI bus BUSY */ 659 #define SXP_PINS_CON_SEL 0x0010 /* SCSI bus SELECT */ 660 #define SXP_PINS_CON_ATN 0x0008 /* SCSI bus ATTENTION */ 661 #define SXP_PINS_CON_MSG 0x0004 /* SCSI bus MESSAGE */ 662 #define SXP_PINS_CON_CD 0x0002 /* SCSI bus COMMAND */ 663 #define SXP_PINS_CON_IO 0x0001 /* SCSI bus INPUT */ 664 665 /* 666 * Set the hold time for the SCSI Bus Reset to be 250 ms 667 */ 668 #define SXP_SCSI_BUS_RESET_HOLD_TIME 250 669 670 /* SXP DIFF PINS REGISTER */ 671 #define SXP_PINS_DIFF_SENSE 0x0200 /* DIFFSENS sig on SCSI bus */ 672 #define SXP_PINS_DIFF_MODE 0x0100 /* DIFFM signal */ 673 #define SXP_PINS_DIFF_ENABLE_OUTPUT 0x0080 /* Enable SXP SCSI data drv */ 674 #define SXP_PINS_DIFF_PINS_MASK 0x007C /* Differential control pins */ 675 #define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */ 676 #define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */ 677 678 /* Ultra2 only */ 679 #define SXP_PINS_LVD_MODE 0x1000 680 #define SXP_PINS_HVD_MODE 0x0800 681 #define SXP_PINS_SE_MODE 0x0400 682 #define SXP_PINS_MODE_MASK (SXP_PINS_LVD_MODE|SXP_PINS_HVD_MODE|SXP_PINS_SE_MODE) 683 684 /* The above have to be put together with the DIFFM pin to make sense */ 685 #define ISP1080_LVD_MODE (SXP_PINS_LVD_MODE) 686 #define ISP1080_HVD_MODE (SXP_PINS_HVD_MODE|SXP_PINS_DIFF_MODE) 687 #define ISP1080_SE_MODE (SXP_PINS_SE_MODE) 688 #define ISP1080_MODE_MASK (SXP_PINS_MODE_MASK|SXP_PINS_DIFF_MODE) 689 690 /* 691 * RISC and Host Command and Control Block Register Offsets 692 */ 693 694 #define RISC_ACC RISC_BLOCK+0x0 /* RW*: Accumulator */ 695 #define RISC_R1 RISC_BLOCK+0x2 /* RW*: GP Reg R1 */ 696 #define RISC_R2 RISC_BLOCK+0x4 /* RW*: GP Reg R2 */ 697 #define RISC_R3 RISC_BLOCK+0x6 /* RW*: GP Reg R3 */ 698 #define RISC_R4 RISC_BLOCK+0x8 /* RW*: GP Reg R4 */ 699 #define RISC_R5 RISC_BLOCK+0xA /* RW*: GP Reg R5 */ 700 #define RISC_R6 RISC_BLOCK+0xC /* RW*: GP Reg R6 */ 701 #define RISC_R7 RISC_BLOCK+0xE /* RW*: GP Reg R7 */ 702 #define RISC_R8 RISC_BLOCK+0x10 /* RW*: GP Reg R8 */ 703 #define RISC_R9 RISC_BLOCK+0x12 /* RW*: GP Reg R9 */ 704 #define RISC_R10 RISC_BLOCK+0x14 /* RW*: GP Reg R10 */ 705 #define RISC_R11 RISC_BLOCK+0x16 /* RW*: GP Reg R11 */ 706 #define RISC_R12 RISC_BLOCK+0x18 /* RW*: GP Reg R12 */ 707 #define RISC_R13 RISC_BLOCK+0x1a /* RW*: GP Reg R13 */ 708 #define RISC_R14 RISC_BLOCK+0x1c /* RW*: GP Reg R14 */ 709 #define RISC_R15 RISC_BLOCK+0x1e /* RW*: GP Reg R15 */ 710 #define RISC_PSR RISC_BLOCK+0x20 /* RW*: Processor Status */ 711 #define RISC_IVR RISC_BLOCK+0x22 /* RW*: Interrupt Vector */ 712 #define RISC_PCR RISC_BLOCK+0x24 /* RW*: Processor Ctrl */ 713 #define RISC_RAR0 RISC_BLOCK+0x26 /* RW*: Ram Address #0 */ 714 #define RISC_RAR1 RISC_BLOCK+0x28 /* RW*: Ram Address #1 */ 715 #define RISC_LCR RISC_BLOCK+0x2a /* RW*: Loop Counter */ 716 #define RISC_PC RISC_BLOCK+0x2c /* R : Program Counter */ 717 #define RISC_MTR RISC_BLOCK+0x2e /* RW*: Memory Timing */ 718 #define RISC_MTR2100 RISC_BLOCK+0x30 719 720 #define RISC_EMB RISC_BLOCK+0x30 /* RW*: Ext Mem Boundary */ 721 #define DUAL_BANK 8 722 #define RISC_SP RISC_BLOCK+0x32 /* RW*: Stack Pointer */ 723 #define RISC_HRL RISC_BLOCK+0x3e /* R *: Hardware Rev Level */ 724 #define HCCR RISC_BLOCK+0x40 /* RW : Host Command & Ctrl */ 725 #define BP0 RISC_BLOCK+0x42 /* RW : Processor Brkpt #0 */ 726 #define BP1 RISC_BLOCK+0x44 /* RW : Processor Brkpt #1 */ 727 #define TCR RISC_BLOCK+0x46 /* W : Test Control */ 728 #define TMR RISC_BLOCK+0x48 /* W : Test Mode */ 729 730 731 /* PROCESSOR STATUS REGISTER */ 732 #define RISC_PSR_FORCE_TRUE 0x8000 733 #define RISC_PSR_LOOP_COUNT_DONE 0x4000 734 #define RISC_PSR_RISC_INT 0x2000 735 #define RISC_PSR_TIMER_ROLLOVER 0x1000 736 #define RISC_PSR_ALU_OVERFLOW 0x0800 737 #define RISC_PSR_ALU_MSB 0x0400 738 #define RISC_PSR_ALU_CARRY 0x0200 739 #define RISC_PSR_ALU_ZERO 0x0100 740 741 #define RISC_PSR_PCI_ULTRA 0x0080 742 #define RISC_PSR_SBUS_ULTRA 0x0020 743 744 #define RISC_PSR_DMA_INT 0x0010 745 #define RISC_PSR_SXP_INT 0x0008 746 #define RISC_PSR_HOST_INT 0x0004 747 #define RISC_PSR_INT_PENDING 0x0002 748 #define RISC_PSR_FORCE_FALSE 0x0001 749 750 751 /* Host Command and Control */ 752 #define HCCR_CMD_NOP 0x0000 /* NOP */ 753 #define HCCR_CMD_RESET 0x1000 /* Reset RISC */ 754 #define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */ 755 #define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */ 756 #define HCCR_CMD_STEP 0x4000 /* Single Step RISC */ 757 #define HCCR_2X00_DISABLE_PARITY_PAUSE 0x4001 /* 758 * Disable RISC pause on FPM 759 * parity error. 760 */ 761 #define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */ 762 #define HCCR_CMD_CLEAR_HOST_INT 0x6000 /* Clear Host Interrupt */ 763 #define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */ 764 #define HCCR_CMD_BREAKPOINT 0x8000 /* Change breakpoint enables */ 765 #define PCI_HCCR_CMD_BIOS 0x9000 /* Write BIOS (disable) */ 766 #define PCI_HCCR_CMD_PARITY 0xA000 /* Write parity enable */ 767 #define PCI_HCCR_CMD_PARITY_ERR 0xE000 /* Generate parity error */ 768 #define HCCR_CMD_TEST_MODE 0xF000 /* Set Test Mode */ 769 770 771 #define ISP2100_HCCR_PARITY_ENABLE_2 0x0400 772 #define ISP2100_HCCR_PARITY_ENABLE_1 0x0200 773 #define ISP2100_HCCR_PARITY_ENABLE_0 0x0100 774 #define ISP2100_HCCR_PARITY 0x0001 775 776 #define PCI_HCCR_PARITY 0x0400 /* Parity error flag */ 777 #define PCI_HCCR_PARITY_ENABLE_1 0x0200 /* Parity enable bank 1 */ 778 #define PCI_HCCR_PARITY_ENABLE_0 0x0100 /* Parity enable bank 0 */ 779 780 #define HCCR_HOST_INT 0x0080 /* R : Host interrupt set */ 781 #define HCCR_RESET 0x0040 /* R : reset in progress */ 782 #define HCCR_PAUSE 0x0020 /* R : RISC paused */ 783 784 #define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */ 785 786 /* 787 * Defines for Interrupts 788 */ 789 #define ISP_INTS_ENABLED(isp) \ 790 ((IS_SCSI(isp))? \ 791 (ISP_READ(isp, BIU_ICR) & BIU_IMASK) : \ 792 (IS_24XX(isp)? (ISP_READ(isp, BIU2400_ICR) & BIU2400_IMASK) : \ 793 (ISP_READ(isp, BIU_ICR) & BIU2100_IMASK))) 794 795 #define ISP_ENABLE_INTS(isp) \ 796 (IS_SCSI(isp) ? \ 797 ISP_WRITE(isp, BIU_ICR, BIU_IMASK) : \ 798 (IS_24XX(isp) ? \ 799 (ISP_WRITE(isp, BIU2400_ICR, BIU2400_IMASK)) : \ 800 (ISP_WRITE(isp, BIU_ICR, BIU2100_IMASK)))) 801 802 #define ISP_DISABLE_INTS(isp) \ 803 IS_24XX(isp)? ISP_WRITE(isp, BIU2400_ICR, 0) : ISP_WRITE(isp, BIU_ICR, 0) 804 805 /* 806 * NVRAM Definitions (PCI cards only) 807 */ 808 809 #define ISPBSMX(c, byte, shift, mask) \ 810 (((c)[(byte)] >> (shift)) & (mask)) 811 /* 812 * Qlogic 1020/1040 NVRAM is an array of 128 bytes. 813 * 814 * Some portion of the front of this is for general host adapter properties 815 * This is followed by an array of per-target parameters, and is tailed off 816 * with a checksum xor byte at offset 127. For non-byte entities data is 817 * stored in Little Endian order. 818 */ 819 820 #define ISP_NVRAM_SIZE 128 821 822 #define ISP_NVRAM_VERSION(c) (c)[4] 823 #define ISP_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 5, 0, 0x03) 824 #define ISP_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 5, 2, 0x01) 825 #define ISP_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 5, 3, 0x01) 826 #define ISP_NVRAM_INITIATOR_ID(c) ISPBSMX(c, 5, 4, 0x0f) 827 #define ISP_NVRAM_BUS_RESET_DELAY(c) (c)[6] 828 #define ISP_NVRAM_BUS_RETRY_COUNT(c) (c)[7] 829 #define ISP_NVRAM_BUS_RETRY_DELAY(c) (c)[8] 830 #define ISP_NVRAM_ASYNC_DATA_SETUP_TIME(c) ISPBSMX(c, 9, 0, 0x0f) 831 #define ISP_NVRAM_REQ_ACK_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 4, 0x01) 832 #define ISP_NVRAM_DATA_LINE_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 5, 0x01) 833 #define ISP_NVRAM_DATA_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 6, 0x01) 834 #define ISP_NVRAM_CMD_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 7, 0x01) 835 #define ISP_NVRAM_TAG_AGE_LIMIT(c) (c)[10] 836 #define ISP_NVRAM_LOWTRM_ENABLE(c) ISPBSMX(c, 11, 0, 0x01) 837 #define ISP_NVRAM_HITRM_ENABLE(c) ISPBSMX(c, 11, 1, 0x01) 838 #define ISP_NVRAM_PCMC_BURST_ENABLE(c) ISPBSMX(c, 11, 2, 0x01) 839 #define ISP_NVRAM_ENABLE_60_MHZ(c) ISPBSMX(c, 11, 3, 0x01) 840 #define ISP_NVRAM_SCSI_RESET_DISABLE(c) ISPBSMX(c, 11, 4, 0x01) 841 #define ISP_NVRAM_ENABLE_AUTO_TERM(c) ISPBSMX(c, 11, 5, 0x01) 842 #define ISP_NVRAM_FIFO_THRESHOLD_128(c) ISPBSMX(c, 11, 6, 0x01) 843 #define ISP_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 11, 7, 0x01) 844 #define ISP_NVRAM_SELECTION_TIMEOUT(c) (((c)[12]) | ((c)[13] << 8)) 845 #define ISP_NVRAM_MAX_QUEUE_DEPTH(c) (((c)[14]) | ((c)[15] << 8)) 846 #define ISP_NVRAM_SCSI_BUS_SIZE(c) ISPBSMX(c, 16, 0, 0x01) 847 #define ISP_NVRAM_SCSI_BUS_TYPE(c) ISPBSMX(c, 16, 1, 0x01) 848 #define ISP_NVRAM_ADAPTER_CLK_SPEED(c) ISPBSMX(c, 16, 2, 0x01) 849 #define ISP_NVRAM_SOFT_TERM_SUPPORT(c) ISPBSMX(c, 16, 3, 0x01) 850 #define ISP_NVRAM_FLASH_ONBOARD(c) ISPBSMX(c, 16, 4, 0x01) 851 #define ISP_NVRAM_FAST_MTTR_ENABLE(c) ISPBSMX(c, 22, 0, 0x01) 852 853 #define ISP_NVRAM_TARGOFF 28 854 #define ISP_NVRAM_TARGSIZE 6 855 #define _IxT(tgt, tidx) \ 856 (ISP_NVRAM_TARGOFF + (ISP_NVRAM_TARGSIZE * (tgt)) + (tidx)) 857 #define ISP_NVRAM_TGT_RENEG(c, t) ISPBSMX(c, _IxT(t, 0), 0, 0x01) 858 #define ISP_NVRAM_TGT_QFRZ(c, t) ISPBSMX(c, _IxT(t, 0), 1, 0x01) 859 #define ISP_NVRAM_TGT_ARQ(c, t) ISPBSMX(c, _IxT(t, 0), 2, 0x01) 860 #define ISP_NVRAM_TGT_TQING(c, t) ISPBSMX(c, _IxT(t, 0), 3, 0x01) 861 #define ISP_NVRAM_TGT_SYNC(c, t) ISPBSMX(c, _IxT(t, 0), 4, 0x01) 862 #define ISP_NVRAM_TGT_WIDE(c, t) ISPBSMX(c, _IxT(t, 0), 5, 0x01) 863 #define ISP_NVRAM_TGT_PARITY(c, t) ISPBSMX(c, _IxT(t, 0), 6, 0x01) 864 #define ISP_NVRAM_TGT_DISC(c, t) ISPBSMX(c, _IxT(t, 0), 7, 0x01) 865 #define ISP_NVRAM_TGT_EXEC_THROTTLE(c, t) ISPBSMX(c, _IxT(t, 1), 0, 0xff) 866 #define ISP_NVRAM_TGT_SYNC_PERIOD(c, t) ISPBSMX(c, _IxT(t, 2), 0, 0xff) 867 #define ISP_NVRAM_TGT_SYNC_OFFSET(c, t) ISPBSMX(c, _IxT(t, 3), 0, 0x0f) 868 #define ISP_NVRAM_TGT_DEVICE_ENABLE(c, t) ISPBSMX(c, _IxT(t, 3), 4, 0x01) 869 #define ISP_NVRAM_TGT_LUN_DISABLE(c, t) ISPBSMX(c, _IxT(t, 3), 5, 0x01) 870 871 /* 872 * Qlogic 1080/1240 NVRAM is an array of 256 bytes. 873 * 874 * Some portion of the front of this is for general host adapter properties 875 * This is followed by an array of per-target parameters, and is tailed off 876 * with a checksum xor byte at offset 256. For non-byte entities data is 877 * stored in Little Endian order. 878 */ 879 880 #define ISP1080_NVRAM_SIZE 256 881 882 #define ISP1080_NVRAM_VERSION(c) ISP_NVRAM_VERSION(c) 883 884 /* Offset 5 */ 885 /* 886 uint8_t bios_configuration_mode :2; 887 uint8_t bios_disable :1; 888 uint8_t selectable_scsi_boot_enable :1; 889 uint8_t cd_rom_boot_enable :1; 890 uint8_t disable_loading_risc_code :1; 891 uint8_t enable_64bit_addressing :1; 892 uint8_t unused_7 :1; 893 */ 894 895 /* Offsets 6, 7 */ 896 /* 897 uint8_t boot_lun_number :5; 898 uint8_t scsi_bus_number :1; 899 uint8_t unused_6 :1; 900 uint8_t unused_7 :1; 901 uint8_t boot_target_number :4; 902 uint8_t unused_12 :1; 903 uint8_t unused_13 :1; 904 uint8_t unused_14 :1; 905 uint8_t unused_15 :1; 906 */ 907 908 #define ISP1080_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 16, 3, 0x01) 909 910 #define ISP1080_NVRAM_BURST_ENABLE(c) ISPBSMX(c, 16, 1, 0x01) 911 #define ISP1080_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 16, 4, 0x0f) 912 913 #define ISP1080_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 17, 7, 0x01) 914 #define ISP1080_NVRAM_BUS0_TERM_MODE(c) ISPBSMX(c, 17, 0, 0x03) 915 #define ISP1080_NVRAM_BUS1_TERM_MODE(c) ISPBSMX(c, 17, 2, 0x03) 916 917 #define ISP1080_ISP_PARAMETER(c) \ 918 (((c)[18]) | ((c)[19] << 8)) 919 920 #define ISP1080_FAST_POST(c) ISPBSMX(c, 20, 0, 0x01) 921 #define ISP1080_REPORT_LVD_TRANSITION(c) ISPBSMX(c, 20, 1, 0x01) 922 923 #define ISP1080_BUS1_OFF 112 924 925 #define ISP1080_NVRAM_INITIATOR_ID(c, b) \ 926 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 24, 0, 0x0f) 927 #define ISP1080_NVRAM_BUS_RESET_DELAY(c, b) \ 928 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 25] 929 #define ISP1080_NVRAM_BUS_RETRY_COUNT(c, b) \ 930 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 26] 931 #define ISP1080_NVRAM_BUS_RETRY_DELAY(c, b) \ 932 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 27] 933 934 #define ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME(c, b) \ 935 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 0, 0x0f) 936 #define ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION(c, b) \ 937 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 4, 0x01) 938 #define ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION(c, b) \ 939 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 5, 0x01) 940 #define ISP1080_NVRAM_SELECTION_TIMEOUT(c, b) \ 941 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 30]) | \ 942 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 31] << 8)) 943 #define ISP1080_NVRAM_MAX_QUEUE_DEPTH(c, b) \ 944 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 32]) | \ 945 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 33] << 8)) 946 947 #define ISP1080_NVRAM_TARGOFF(b) \ 948 ((b == 0)? 40: (40 + ISP1080_BUS1_OFF)) 949 #define ISP1080_NVRAM_TARGSIZE 6 950 #define _IxT8(tgt, tidx, b) \ 951 (ISP1080_NVRAM_TARGOFF((b)) + (ISP1080_NVRAM_TARGSIZE * (tgt)) + (tidx)) 952 953 #define ISP1080_NVRAM_TGT_RENEG(c, t, b) \ 954 ISPBSMX(c, _IxT8(t, 0, (b)), 0, 0x01) 955 #define ISP1080_NVRAM_TGT_QFRZ(c, t, b) \ 956 ISPBSMX(c, _IxT8(t, 0, (b)), 1, 0x01) 957 #define ISP1080_NVRAM_TGT_ARQ(c, t, b) \ 958 ISPBSMX(c, _IxT8(t, 0, (b)), 2, 0x01) 959 #define ISP1080_NVRAM_TGT_TQING(c, t, b) \ 960 ISPBSMX(c, _IxT8(t, 0, (b)), 3, 0x01) 961 #define ISP1080_NVRAM_TGT_SYNC(c, t, b) \ 962 ISPBSMX(c, _IxT8(t, 0, (b)), 4, 0x01) 963 #define ISP1080_NVRAM_TGT_WIDE(c, t, b) \ 964 ISPBSMX(c, _IxT8(t, 0, (b)), 5, 0x01) 965 #define ISP1080_NVRAM_TGT_PARITY(c, t, b) \ 966 ISPBSMX(c, _IxT8(t, 0, (b)), 6, 0x01) 967 #define ISP1080_NVRAM_TGT_DISC(c, t, b) \ 968 ISPBSMX(c, _IxT8(t, 0, (b)), 7, 0x01) 969 #define ISP1080_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ 970 ISPBSMX(c, _IxT8(t, 1, (b)), 0, 0xff) 971 #define ISP1080_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ 972 ISPBSMX(c, _IxT8(t, 2, (b)), 0, 0xff) 973 #define ISP1080_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ 974 ISPBSMX(c, _IxT8(t, 3, (b)), 0, 0x0f) 975 #define ISP1080_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ 976 ISPBSMX(c, _IxT8(t, 3, (b)), 4, 0x01) 977 #define ISP1080_NVRAM_TGT_LUN_DISABLE(c, t, b) \ 978 ISPBSMX(c, _IxT8(t, 3, (b)), 5, 0x01) 979 980 #define ISP12160_NVRAM_HBA_ENABLE ISP1080_NVRAM_HBA_ENABLE 981 #define ISP12160_NVRAM_BURST_ENABLE ISP1080_NVRAM_BURST_ENABLE 982 #define ISP12160_NVRAM_FIFO_THRESHOLD ISP1080_NVRAM_FIFO_THRESHOLD 983 #define ISP12160_NVRAM_AUTO_TERM_SUPPORT ISP1080_NVRAM_AUTO_TERM_SUPPORT 984 #define ISP12160_NVRAM_BUS0_TERM_MODE ISP1080_NVRAM_BUS0_TERM_MODE 985 #define ISP12160_NVRAM_BUS1_TERM_MODE ISP1080_NVRAM_BUS1_TERM_MODE 986 #define ISP12160_ISP_PARAMETER ISP12160_ISP_PARAMETER 987 #define ISP12160_FAST_POST ISP1080_FAST_POST 988 #define ISP12160_REPORT_LVD_TRANSITION ISP1080_REPORT_LVD_TRANSTION 989 990 #define ISP12160_NVRAM_INITIATOR_ID \ 991 ISP1080_NVRAM_INITIATOR_ID 992 #define ISP12160_NVRAM_BUS_RESET_DELAY \ 993 ISP1080_NVRAM_BUS_RESET_DELAY 994 #define ISP12160_NVRAM_BUS_RETRY_COUNT \ 995 ISP1080_NVRAM_BUS_RETRY_COUNT 996 #define ISP12160_NVRAM_BUS_RETRY_DELAY \ 997 ISP1080_NVRAM_BUS_RETRY_DELAY 998 #define ISP12160_NVRAM_ASYNC_DATA_SETUP_TIME \ 999 ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME 1000 #define ISP12160_NVRAM_REQ_ACK_ACTIVE_NEGATION \ 1001 ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION 1002 #define ISP12160_NVRAM_DATA_LINE_ACTIVE_NEGATION \ 1003 ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION 1004 #define ISP12160_NVRAM_SELECTION_TIMEOUT \ 1005 ISP1080_NVRAM_SELECTION_TIMEOUT 1006 #define ISP12160_NVRAM_MAX_QUEUE_DEPTH \ 1007 ISP1080_NVRAM_MAX_QUEUE_DEPTH 1008 1009 1010 #define ISP12160_BUS0_OFF 24 1011 #define ISP12160_BUS1_OFF 136 1012 1013 #define ISP12160_NVRAM_TARGOFF(b) \ 1014 (((b == 0)? ISP12160_BUS0_OFF : ISP12160_BUS1_OFF) + 16) 1015 1016 #define ISP12160_NVRAM_TARGSIZE 6 1017 #define _IxT16(tgt, tidx, b) \ 1018 (ISP12160_NVRAM_TARGOFF((b))+(ISP12160_NVRAM_TARGSIZE * (tgt))+(tidx)) 1019 1020 #define ISP12160_NVRAM_TGT_RENEG(c, t, b) \ 1021 ISPBSMX(c, _IxT16(t, 0, (b)), 0, 0x01) 1022 #define ISP12160_NVRAM_TGT_QFRZ(c, t, b) \ 1023 ISPBSMX(c, _IxT16(t, 0, (b)), 1, 0x01) 1024 #define ISP12160_NVRAM_TGT_ARQ(c, t, b) \ 1025 ISPBSMX(c, _IxT16(t, 0, (b)), 2, 0x01) 1026 #define ISP12160_NVRAM_TGT_TQING(c, t, b) \ 1027 ISPBSMX(c, _IxT16(t, 0, (b)), 3, 0x01) 1028 #define ISP12160_NVRAM_TGT_SYNC(c, t, b) \ 1029 ISPBSMX(c, _IxT16(t, 0, (b)), 4, 0x01) 1030 #define ISP12160_NVRAM_TGT_WIDE(c, t, b) \ 1031 ISPBSMX(c, _IxT16(t, 0, (b)), 5, 0x01) 1032 #define ISP12160_NVRAM_TGT_PARITY(c, t, b) \ 1033 ISPBSMX(c, _IxT16(t, 0, (b)), 6, 0x01) 1034 #define ISP12160_NVRAM_TGT_DISC(c, t, b) \ 1035 ISPBSMX(c, _IxT16(t, 0, (b)), 7, 0x01) 1036 1037 #define ISP12160_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ 1038 ISPBSMX(c, _IxT16(t, 1, (b)), 0, 0xff) 1039 #define ISP12160_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ 1040 ISPBSMX(c, _IxT16(t, 2, (b)), 0, 0xff) 1041 1042 #define ISP12160_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ 1043 ISPBSMX(c, _IxT16(t, 3, (b)), 0, 0x1f) 1044 #define ISP12160_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ 1045 ISPBSMX(c, _IxT16(t, 3, (b)), 5, 0x01) 1046 1047 #define ISP12160_NVRAM_PPR_OPTIONS(c, t, b) \ 1048 ISPBSMX(c, _IxT16(t, 4, (b)), 0, 0x0f) 1049 #define ISP12160_NVRAM_PPR_WIDTH(c, t, b) \ 1050 ISPBSMX(c, _IxT16(t, 4, (b)), 4, 0x03) 1051 #define ISP12160_NVRAM_PPR_ENABLE(c, t, b) \ 1052 ISPBSMX(c, _IxT16(t, 4, (b)), 7, 0x01) 1053 1054 /* 1055 * Qlogic 2100 thru 2300 NVRAM is an array of 256 bytes. 1056 * 1057 * Some portion of the front of this is for general RISC engine parameters, 1058 * mostly reflecting the state of the last INITIALIZE FIRMWARE mailbox command. 1059 * 1060 * This is followed by some general host adapter parameters, and ends with 1061 * a checksum xor byte at offset 255. For non-byte entities data is stored 1062 * in Little Endian order. 1063 */ 1064 #define ISP2100_NVRAM_SIZE 256 1065 /* ISP_NVRAM_VERSION is in same overall place */ 1066 #define ISP2100_NVRAM_RISCVER(c) (c)[6] 1067 #define ISP2100_NVRAM_OPTIONS(c) ((c)[8] | ((c)[9] << 8)) 1068 #define ISP2100_NVRAM_MAXFRAMELENGTH(c) (((c)[10]) | ((c)[11] << 8)) 1069 #define ISP2100_NVRAM_MAXIOCBALLOCATION(c) (((c)[12]) | ((c)[13] << 8)) 1070 #define ISP2100_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8)) 1071 #define ISP2100_NVRAM_RETRY_COUNT(c) (c)[16] 1072 #define ISP2100_NVRAM_RETRY_DELAY(c) (c)[17] 1073 1074 #define ISP2100_NVRAM_PORT_NAME(c) (\ 1075 (((uint64_t)(c)[18]) << 56) | \ 1076 (((uint64_t)(c)[19]) << 48) | \ 1077 (((uint64_t)(c)[20]) << 40) | \ 1078 (((uint64_t)(c)[21]) << 32) | \ 1079 (((uint64_t)(c)[22]) << 24) | \ 1080 (((uint64_t)(c)[23]) << 16) | \ 1081 (((uint64_t)(c)[24]) << 8) | \ 1082 (((uint64_t)(c)[25]) << 0)) 1083 1084 #define ISP2100_NVRAM_HARDLOOPID(c) ((c)[26] | ((c)[27] << 8)) 1085 #define ISP2100_NVRAM_TOV(c) ((c)[29]) 1086 1087 #define ISP2100_NVRAM_NODE_NAME(c) (\ 1088 (((uint64_t)(c)[30]) << 56) | \ 1089 (((uint64_t)(c)[31]) << 48) | \ 1090 (((uint64_t)(c)[32]) << 40) | \ 1091 (((uint64_t)(c)[33]) << 32) | \ 1092 (((uint64_t)(c)[34]) << 24) | \ 1093 (((uint64_t)(c)[35]) << 16) | \ 1094 (((uint64_t)(c)[36]) << 8) | \ 1095 (((uint64_t)(c)[37]) << 0)) 1096 1097 #define ISP2100_XFW_OPTIONS(c) ((c)[38] | ((c)[39] << 8)) 1098 1099 #define ISP2100_RACC_TIMER(c) (c)[40] 1100 #define ISP2100_IDELAY_TIMER(c) (c)[41] 1101 1102 #define ISP2100_ZFW_OPTIONS(c) ((c)[42] | ((c)[43] << 8)) 1103 1104 #define ISP2100_SERIAL_LINK(c) ((c)[68] | ((c)[69] << 8)) 1105 1106 #define ISP2100_NVRAM_HBA_OPTIONS(c) ((c)[70] | ((c)[71] << 8)) 1107 #define ISP2100_NVRAM_HBA_DISABLE(c) ISPBSMX(c, 70, 0, 0x01) 1108 #define ISP2100_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 70, 1, 0x01) 1109 #define ISP2100_NVRAM_LUN_DISABLE(c) ISPBSMX(c, 70, 2, 0x01) 1110 #define ISP2100_NVRAM_ENABLE_SELECT_BOOT(c) ISPBSMX(c, 70, 3, 0x01) 1111 #define ISP2100_NVRAM_DISABLE_CODELOAD(c) ISPBSMX(c, 70, 4, 0x01) 1112 #define ISP2100_NVRAM_SET_CACHELINESZ(c) ISPBSMX(c, 70, 5, 0x01) 1113 1114 #define ISP2100_NVRAM_BOOT_NODE_NAME(c) (\ 1115 (((uint64_t)(c)[72]) << 56) | \ 1116 (((uint64_t)(c)[73]) << 48) | \ 1117 (((uint64_t)(c)[74]) << 40) | \ 1118 (((uint64_t)(c)[75]) << 32) | \ 1119 (((uint64_t)(c)[76]) << 24) | \ 1120 (((uint64_t)(c)[77]) << 16) | \ 1121 (((uint64_t)(c)[78]) << 8) | \ 1122 (((uint64_t)(c)[79]) << 0)) 1123 1124 #define ISP2100_NVRAM_BOOT_LUN(c) (c)[80] 1125 #define ISP2100_RESET_DELAY(c) (c)[81] 1126 1127 #define ISP2100_HBA_FEATURES(c) ((c)[232] | ((c)[233] << 8)) 1128 1129 /* 1130 * Qlogic 2400 NVRAM is an array of 512 bytes with a 32 bit checksum. 1131 */ 1132 #define ISP2400_NVRAM_PORT0_ADDR 0x80 1133 #define ISP2400_NVRAM_PORT1_ADDR 0x180 1134 #define ISP2400_NVRAM_SIZE 512 1135 1136 #define ISP2400_NVRAM_VERSION(c) ((c)[4] | ((c)[5] << 8)) 1137 #define ISP2400_NVRAM_MAXFRAMELENGTH(c) (((c)[12]) | ((c)[13] << 8)) 1138 #define ISP2400_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8)) 1139 #define ISP2400_NVRAM_EXCHANGE_COUNT(c) (((c)[16]) | ((c)[17] << 8)) 1140 #define ISP2400_NVRAM_HARDLOOPID(c) ((c)[18] | ((c)[19] << 8)) 1141 1142 #define ISP2400_NVRAM_PORT_NAME(c) (\ 1143 (((uint64_t)(c)[20]) << 56) | \ 1144 (((uint64_t)(c)[21]) << 48) | \ 1145 (((uint64_t)(c)[22]) << 40) | \ 1146 (((uint64_t)(c)[23]) << 32) | \ 1147 (((uint64_t)(c)[24]) << 24) | \ 1148 (((uint64_t)(c)[25]) << 16) | \ 1149 (((uint64_t)(c)[26]) << 8) | \ 1150 (((uint64_t)(c)[27]) << 0)) 1151 1152 #define ISP2400_NVRAM_NODE_NAME(c) (\ 1153 (((uint64_t)(c)[28]) << 56) | \ 1154 (((uint64_t)(c)[29]) << 48) | \ 1155 (((uint64_t)(c)[30]) << 40) | \ 1156 (((uint64_t)(c)[31]) << 32) | \ 1157 (((uint64_t)(c)[32]) << 24) | \ 1158 (((uint64_t)(c)[33]) << 16) | \ 1159 (((uint64_t)(c)[34]) << 8) | \ 1160 (((uint64_t)(c)[35]) << 0)) 1161 1162 #define ISP2400_NVRAM_LOGIN_RETRY_CNT(c) ((c)[36] | ((c)[37] << 8)) 1163 #define ISP2400_NVRAM_LINK_DOWN_ON_NOS(c) ((c)[38] | ((c)[39] << 8)) 1164 #define ISP2400_NVRAM_INTERRUPT_DELAY(c) ((c)[40] | ((c)[41] << 8)) 1165 #define ISP2400_NVRAM_LOGIN_TIMEOUT(c) ((c)[42] | ((c)[43] << 8)) 1166 1167 #define ISP2400_NVRAM_FIRMWARE_OPTIONS1(c) \ 1168 ((c)[44] | ((c)[45] << 8) | ((c)[46] << 16) | ((c)[47] << 24)) 1169 #define ISP2400_NVRAM_FIRMWARE_OPTIONS2(c) \ 1170 ((c)[48] | ((c)[49] << 8) | ((c)[50] << 16) | ((c)[51] << 24)) 1171 #define ISP2400_NVRAM_FIRMWARE_OPTIONS3(c) \ 1172 ((c)[52] | ((c)[53] << 8) | ((c)[54] << 16) | ((c)[55] << 24)) 1173 1174 /* 1175 * Firmware Crash Dump 1176 * 1177 * QLogic needs specific information format when they look at firmware crashes. 1178 * 1179 * This is incredibly kernel memory consumptive (to say the least), so this 1180 * code is only compiled in when needed. 1181 */ 1182 1183 #define QLA2200_RISC_IMAGE_DUMP_SIZE \ 1184 (1 * sizeof (uint16_t)) + /* 'used' flag (also HBA type) */ \ 1185 (352 * sizeof (uint16_t)) + /* RISC registers */ \ 1186 (61440 * sizeof (uint16_t)) /* RISC SRAM (offset 0x1000..0xffff) */ 1187 #define QLA2300_RISC_IMAGE_DUMP_SIZE \ 1188 (1 * sizeof (uint16_t)) + /* 'used' flag (also HBA type) */ \ 1189 (464 * sizeof (uint16_t)) + /* RISC registers */ \ 1190 (63488 * sizeof (uint16_t)) + /* RISC SRAM (0x0800..0xffff) */ \ 1191 (4096 * sizeof (uint16_t)) + /* RISC SRAM (0x10000..0x10FFF) */ \ 1192 (61440 * sizeof (uint16_t)) /* RISC SRAM (0x11000..0x1FFFF) */ 1193 /* the larger of the two */ 1194 #define ISP_CRASH_IMAGE_SIZE QLA2300_RISC_IMAGE_DUMP_SIZE 1195 #endif /* _ISPREG_H */ 1196
Indexes created Sun Sep 21 19:09:51 GMT 2025