1 /* $NetBSD: rk3288_cru.h,v 1.1 2021/11/12 22:02:08 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2021 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _RK3328_CRU_H 30 #define _RK3328_CRU_H 31 32 #define RK3288_PLL_APLL 1 33 #define RK3288_PLL_DPLL 2 34 #define RK3288_PLL_CPLL 3 35 #define RK3288_PLL_GPLL 4 36 #define RK3288_PLL_NPLL 5 37 #define RK3288_ARMCLK 6 38 #define RK3288_SCLK_GPU 64 39 #define RK3288_SCLK_SPI0 65 40 #define RK3288_SCLK_SPI1 66 41 #define RK3288_SCLK_SPI2 67 42 #define RK3288_SCLK_SDMMC 68 43 #define RK3288_SCLK_SDIO0 69 44 #define RK3288_SCLK_SDIO1 70 45 #define RK3288_SCLK_EMMC 71 46 #define RK3288_SCLK_TSADC 72 47 #define RK3288_SCLK_SARADC 73 48 #define RK3288_SCLK_PS2C 74 49 #define RK3288_SCLK_NANDC0 75 50 #define RK3288_SCLK_NANDC1 76 51 #define RK3288_SCLK_UART0 77 52 #define RK3288_SCLK_UART1 78 53 #define RK3288_SCLK_UART2 79 54 #define RK3288_SCLK_UART3 80 55 #define RK3288_SCLK_UART4 81 56 #define RK3288_SCLK_I2S0 82 57 #define RK3288_SCLK_SPDIF 83 58 #define RK3288_SCLK_SPDIF8CH 84 59 #define RK3288_SCLK_TIMER0 85 60 #define RK3288_SCLK_TIMER1 86 61 #define RK3288_SCLK_TIMER2 87 62 #define RK3288_SCLK_TIMER3 88 63 #define RK3288_SCLK_TIMER4 89 64 #define RK3288_SCLK_TIMER5 90 65 #define RK3288_SCLK_TIMER6 91 66 #define RK3288_SCLK_HSADC 92 67 #define RK3288_SCLK_OTGPHY0 93 68 #define RK3288_SCLK_OTGPHY1 94 69 #define RK3288_SCLK_OTGPHY2 95 70 #define RK3288_SCLK_OTG_ADP 96 71 #define RK3288_SCLK_HSICPHY480M 97 72 #define RK3288_SCLK_HSICPHY12M 98 73 #define RK3288_SCLK_MACREF 99 74 #define RK3288_SCLK_LCDC_PWM0 100 75 #define RK3288_SCLK_LCDC_PWM1 101 76 #define RK3288_SCLK_MAC_RX 102 77 #define RK3288_SCLK_MAC_TX 103 78 #define RK3288_SCLK_EDP_24M 104 79 #define RK3288_SCLK_EDP 105 80 #define RK3288_SCLK_RGA 106 81 #define RK3288_SCLK_ISP 107 82 #define RK3288_SCLK_ISP_JPE 108 83 #define RK3288_SCLK_HDMI_HDCP 109 84 #define RK3288_SCLK_HDMI_CEC 110 85 #define RK3288_SCLK_HEVC_CABAC 111 86 #define RK3288_SCLK_HEVC_CORE 112 87 #define RK3288_SCLK_I2S0_OUT 113 88 #define RK3288_SCLK_SDMMC_DRV 114 89 #define RK3288_SCLK_SDIO0_DRV 115 90 #define RK3288_SCLK_SDIO1_DRV 116 91 #define RK3288_SCLK_EMMC_DRV 117 92 #define RK3288_SCLK_SDMMC_SAMPLE 118 93 #define RK3288_SCLK_SDIO0_SAMPLE 119 94 #define RK3288_SCLK_SDIO1_SAMPLE 120 95 #define RK3288_SCLK_EMMC_SAMPLE 121 96 #define RK3288_SCLK_USBPHY480M_SRC 122 97 #define RK3288_SCLK_PVTM_CORE 123 98 #define RK3288_SCLK_PVTM_GPU 124 99 #define RK3288_SCLK_CRYPTO 125 100 #define RK3288_SCLK_MIPIDSI_24M 126 101 #define RK3288_SCLK_VIP_OUT 127 102 #define RK3288_SCLK_MAC 151 103 #define RK3288_SCLK_MACREF_OUT 152 104 #define RK3288_DCLK_VOP0 190 105 #define RK3288_DCLK_VOP1 191 106 #define RK3288_ACLK_GPU 192 107 #define RK3288_ACLK_DMAC1 193 108 #define RK3288_ACLK_DMAC2 194 109 #define RK3288_ACLK_MMU 195 110 #define RK3288_ACLK_GMAC 196 111 #define RK3288_ACLK_VOP0 197 112 #define RK3288_ACLK_VOP1 198 113 #define RK3288_ACLK_CRYPTO 199 114 #define RK3288_ACLK_RGA 200 115 #define RK3288_ACLK_RGA_NIU 201 116 #define RK3288_ACLK_IEP 202 117 #define RK3288_ACLK_VIO0_NIU 203 118 #define RK3288_ACLK_VIP 204 119 #define RK3288_ACLK_ISP 205 120 #define RK3288_ACLK_VIO1_NIU 206 121 #define RK3288_ACLK_HEVC 207 122 #define RK3288_ACLK_VCODEC 208 123 #define RK3288_ACLK_CPU 209 124 #define RK3288_ACLK_PERI 210 125 #define RK3288_PCLK_GPIO0 320 126 #define RK3288_PCLK_GPIO1 321 127 #define RK3288_PCLK_GPIO2 322 128 #define RK3288_PCLK_GPIO3 323 129 #define RK3288_PCLK_GPIO4 324 130 #define RK3288_PCLK_GPIO5 325 131 #define RK3288_PCLK_GPIO6 326 132 #define RK3288_PCLK_GPIO7 327 133 #define RK3288_PCLK_GPIO8 328 134 #define RK3288_PCLK_GRF 329 135 #define RK3288_PCLK_SGRF 330 136 #define RK3288_PCLK_PMU 331 137 #define RK3288_PCLK_I2C0 332 138 #define RK3288_PCLK_I2C1 333 139 #define RK3288_PCLK_I2C2 334 140 #define RK3288_PCLK_I2C3 335 141 #define RK3288_PCLK_I2C4 336 142 #define RK3288_PCLK_I2C5 337 143 #define RK3288_PCLK_SPI0 338 144 #define RK3288_PCLK_SPI1 339 145 #define RK3288_PCLK_SPI2 340 146 #define RK3288_PCLK_UART0 341 147 #define RK3288_PCLK_UART1 342 148 #define RK3288_PCLK_UART2 343 149 #define RK3288_PCLK_UART3 344 150 #define RK3288_PCLK_UART4 345 151 #define RK3288_PCLK_TSADC 346 152 #define RK3288_PCLK_SARADC 347 153 #define RK3288_PCLK_SIM 348 154 #define RK3288_PCLK_GMAC 349 155 #define RK3288_PCLK_PWM 350 156 #define RK3288_PCLK_RKPWM 351 157 #define RK3288_PCLK_PS2C 352 158 #define RK3288_PCLK_TIMER 353 159 #define RK3288_PCLK_TZPC 354 160 #define RK3288_PCLK_EDP_CTRL 355 161 #define RK3288_PCLK_MIPI_DSI0 356 162 #define RK3288_PCLK_MIPI_DSI1 357 163 #define RK3288_PCLK_MIPI_CSI 358 164 #define RK3288_PCLK_LVDS_PHY 359 165 #define RK3288_PCLK_HDMI_CTRL 360 166 #define RK3288_PCLK_VIO2_H2P 361 167 #define RK3288_PCLK_CPU 362 168 #define RK3288_PCLK_PERI 363 169 #define RK3288_PCLK_DDRUPCTL0 364 170 #define RK3288_PCLK_PUBL0 365 171 #define RK3288_PCLK_DDRUPCTL1 366 172 #define RK3288_PCLK_PUBL1 367 173 #define RK3288_PCLK_WDT 368 174 #define RK3288_PCLK_EFUSE256 369 175 #define RK3288_PCLK_EFUSE1024 370 176 #define RK3288_PCLK_ISP_IN 371 177 #define RK3288_HCLK_GPS 448 178 #define RK3288_HCLK_OTG0 449 179 #define RK3288_HCLK_USBHOST0 450 180 #define RK3288_HCLK_USBHOST1 451 181 #define RK3288_HCLK_HSIC 452 182 #define RK3288_HCLK_NANDC0 453 183 #define RK3288_HCLK_NANDC1 454 184 #define RK3288_HCLK_TSP 455 185 #define RK3288_HCLK_SDMMC 456 186 #define RK3288_HCLK_SDIO0 457 187 #define RK3288_HCLK_SDIO1 458 188 #define RK3288_HCLK_EMMC 459 189 #define RK3288_HCLK_HSADC 460 190 #define RK3288_HCLK_CRYPTO 461 191 #define RK3288_HCLK_I2S0 462 192 #define RK3288_HCLK_SPDIF 463 193 #define RK3288_HCLK_SPDIF8CH 464 194 #define RK3288_HCLK_VOP0 465 195 #define RK3288_HCLK_VOP1 466 196 #define RK3288_HCLK_ROM 467 197 #define RK3288_HCLK_IEP 468 198 #define RK3288_HCLK_ISP 469 199 #define RK3288_HCLK_RGA 470 200 #define RK3288_HCLK_VIO_AHB_ARBI 471 201 #define RK3288_HCLK_VIO_NIU 472 202 #define RK3288_HCLK_VIP 473 203 #define RK3288_HCLK_VIO2_H2P 474 204 #define RK3288_HCLK_HEVC 475 205 #define RK3288_HCLK_VCODEC 476 206 #define RK3288_HCLK_CPU 477 207 #define RK3288_HCLK_PERI 478 208 209 #endif /* !_RK3328_CRU_H */ 210
Indexes created Tue Sep 23 07:09:52 GMT 2025