1 /* $NetBSD: rk3328_cru.h,v 1.2 2020/12/31 11:36:12 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _RK3328_CRU_H 30 #define _RK3328_CRU_H 31 32 #define RK3328_PLL_APLL 1 33 #define RK3328_PLL_DPLL 2 34 #define RK3328_PLL_CPLL 3 35 #define RK3328_PLL_GPLL 4 36 #define RK3328_PLL_NPLL 5 37 #define RK3328_ARMCLK 6 38 #define RK3328_SCLK_RTC32K 30 39 #define RK3328_SCLK_SDMMC_EXT 31 40 #define RK3328_SCLK_SPI 32 41 #define RK3328_SCLK_SDMMC 33 42 #define RK3328_SCLK_SDIO 34 43 #define RK3328_SCLK_EMMC 35 44 #define RK3328_SCLK_TSADC 36 45 #define RK3328_SCLK_SARADC 37 46 #define RK3328_SCLK_UART0 38 47 #define RK3328_SCLK_UART1 39 48 #define RK3328_SCLK_UART2 40 49 #define RK3328_SCLK_I2S0 41 50 #define RK3328_SCLK_I2S1 42 51 #define RK3328_SCLK_I2S2 43 52 #define RK3328_SCLK_I2S1_OUT 44 53 #define RK3328_SCLK_I2S2_OUT 45 54 #define RK3328_SCLK_SPDIF 46 55 #define RK3328_SCLK_TIMER0 47 56 #define RK3328_SCLK_TIMER1 48 57 #define RK3328_SCLK_TIMER2 49 58 #define RK3328_SCLK_TIMER3 50 59 #define RK3328_SCLK_TIMER4 51 60 #define RK3328_SCLK_TIMER5 52 61 #define RK3328_SCLK_WIFI 53 62 #define RK3328_SCLK_CIF_OUT 54 63 #define RK3328_SCLK_I2C0 55 64 #define RK3328_SCLK_I2C1 56 65 #define RK3328_SCLK_I2C2 57 66 #define RK3328_SCLK_I2C3 58 67 #define RK3328_SCLK_CRYPTO 59 68 #define RK3328_SCLK_PWM 60 69 #define RK3328_SCLK_PDM 61 70 #define RK3328_SCLK_EFUSE 62 71 #define RK3328_SCLK_OTP 63 72 #define RK3328_SCLK_DDRCLK 64 73 #define RK3328_SCLK_VDEC_CABAC 65 74 #define RK3328_SCLK_VDEC_CORE 66 75 #define RK3328_SCLK_VENC_DSP 67 76 #define RK3328_SCLK_VENC_CORE 68 77 #define RK3328_SCLK_RGA 69 78 #define RK3328_SCLK_HDMI_SFC 70 79 #define RK3328_SCLK_HDMI_CEC 71 80 #define RK3328_SCLK_USB3_REF 72 81 #define RK3328_SCLK_USB3_SUSPEND 73 82 #define RK3328_SCLK_SDMMC_DRV 74 83 #define RK3328_SCLK_SDIO_DRV 75 84 #define RK3328_SCLK_EMMC_DRV 76 85 #define RK3328_SCLK_SDMMC_EXT_DRV 77 86 #define RK3328_SCLK_SDMMC_SAMPLE 78 87 #define RK3328_SCLK_SDIO_SAMPLE 79 88 #define RK3328_SCLK_EMMC_SAMPLE 80 89 #define RK3328_SCLK_SDMMC_EXT_SAMPLE 81 90 #define RK3328_SCLK_VOP 82 91 #define RK3328_SCLK_MAC2PHY_RXTX 83 92 #define RK3328_SCLK_MAC2PHY_SRC 84 93 #define RK3328_SCLK_MAC2PHY_REF 85 94 #define RK3328_SCLK_MAC2PHY_OUT 86 95 #define RK3328_SCLK_MAC2IO_RX 87 96 #define RK3328_SCLK_MAC2IO_TX 88 97 #define RK3328_SCLK_MAC2IO_REFOUT 89 98 #define RK3328_SCLK_MAC2IO_REF 90 99 #define RK3328_SCLK_MAC2IO_OUT 91 100 #define RK3328_SCLK_TSP 92 101 #define RK3328_SCLK_HSADC_TSP 93 102 #define RK3328_SCLK_USB3PHY_REF 94 103 #define RK3328_SCLK_REF_USB3OTG 95 104 #define RK3328_SCLK_USB3OTG_REF 96 105 #define RK3328_SCLK_USB3OTG_SUSPEND 97 106 #define RK3328_SCLK_REF_USB3OTG_SRC 98 107 #define RK3328_SCLK_MAC2IO_SRC 99 108 #define RK3328_SCLK_MAC2IO 100 109 #define RK3328_SCLK_MAC2PHY 101 110 #define RK3328_SCLK_MAC2IO_EXT 102 111 #define RK3328_DCLK_LCDC 120 112 #define RK3328_DCLK_HDMIPHY 121 113 #define RK3328_HDMIPHY 122 114 #define RK3328_USB480M 123 115 #define RK3328_DCLK_LCDC_SRC 124 116 #define RK3328_ACLK_AXISRAM 130 117 #define RK3328_ACLK_VOP_PRE 131 118 #define RK3328_ACLK_USB3OTG 132 119 #define RK3328_ACLK_RGA_PRE 133 120 #define RK3328_ACLK_DMAC 134 121 #define RK3328_ACLK_GPU 135 122 #define RK3328_ACLK_BUS_PRE 136 123 #define RK3328_ACLK_PERI_PRE 137 124 #define RK3328_ACLK_RKVDEC_PRE 138 125 #define RK3328_ACLK_RKVDEC 139 126 #define RK3328_ACLK_RKVENC 140 127 #define RK3328_ACLK_VPU_PRE 141 128 #define RK3328_ACLK_VIO_PRE 142 129 #define RK3328_ACLK_VPU 143 130 #define RK3328_ACLK_VIO 144 131 #define RK3328_ACLK_VOP 145 132 #define RK3328_ACLK_GMAC 146 133 #define RK3328_ACLK_H265 147 134 #define RK3328_ACLK_H264 148 135 #define RK3328_ACLK_MAC2PHY 149 136 #define RK3328_ACLK_MAC2IO 150 137 #define RK3328_ACLK_DCF 151 138 #define RK3328_ACLK_TSP 152 139 #define RK3328_ACLK_PERI 153 140 #define RK3328_ACLK_RGA 154 141 #define RK3328_ACLK_IEP 155 142 #define RK3328_ACLK_CIF 156 143 #define RK3328_ACLK_HDCP 157 144 #define RK3328_PCLK_GPIO0 200 145 #define RK3328_PCLK_GPIO1 201 146 #define RK3328_PCLK_GPIO2 202 147 #define RK3328_PCLK_GPIO3 203 148 #define RK3328_PCLK_GRF 204 149 #define RK3328_PCLK_I2C0 205 150 #define RK3328_PCLK_I2C1 206 151 #define RK3328_PCLK_I2C2 207 152 #define RK3328_PCLK_I2C3 208 153 #define RK3328_PCLK_SPI 209 154 #define RK3328_PCLK_UART0 210 155 #define RK3328_PCLK_UART1 211 156 #define RK3328_PCLK_UART2 212 157 #define RK3328_PCLK_TSADC 213 158 #define RK3328_PCLK_PWM 214 159 #define RK3328_PCLK_TIMER 215 160 #define RK3328_PCLK_BUS_PRE 216 161 #define RK3328_PCLK_PERI_PRE 217 162 #define RK3328_PCLK_HDMI_CTRL 218 163 #define RK3328_PCLK_HDMI_PHY 219 164 #define RK3328_PCLK_GMAC 220 165 #define RK3328_PCLK_H265 221 166 #define RK3328_PCLK_MAC2PHY 222 167 #define RK3328_PCLK_MAC2IO 223 168 #define RK3328_PCLK_USB3PHY_OTG 224 169 #define RK3328_PCLK_USB3PHY_PIPE 225 170 #define RK3328_PCLK_USB3_GRF 226 171 #define RK3328_PCLK_USB2_GRF 227 172 #define RK3328_PCLK_HDMIPHY 228 173 #define RK3328_PCLK_DDR 229 174 #define RK3328_PCLK_PERI 230 175 #define RK3328_PCLK_HDMI 231 176 #define RK3328_PCLK_HDCP 232 177 #define RK3328_PCLK_DCF 233 178 #define RK3328_PCLK_SARADC 234 179 #define RK3328_HCLK_PERI 308 180 #define RK3328_HCLK_TSP 309 181 #define RK3328_HCLK_GMAC 310 182 #define RK3328_HCLK_I2S0_8CH 311 183 #define RK3328_HCLK_I2S1_8CH 312 184 #define RK3328_HCLK_I2S2_2CH 313 185 #define RK3328_HCLK_SPDIF_8CH 314 186 #define RK3328_HCLK_VOP 315 187 #define RK3328_HCLK_NANDC 316 188 #define RK3328_HCLK_SDMMC 317 189 #define RK3328_HCLK_SDIO 318 190 #define RK3328_HCLK_EMMC 319 191 #define RK3328_HCLK_SDMMC_EXT 320 192 #define RK3328_HCLK_RKVDEC_PRE 321 193 #define RK3328_HCLK_RKVDEC 322 194 #define RK3328_HCLK_RKVENC 323 195 #define RK3328_HCLK_VPU_PRE 324 196 #define RK3328_HCLK_VIO_PRE 325 197 #define RK3328_HCLK_VPU 326 198 #define RK3328_HCLK_BUS_PRE 328 199 #define RK3328_HCLK_PERI_PRE 329 200 #define RK3328_HCLK_H264 330 201 #define RK3328_HCLK_CIF 331 202 #define RK3328_HCLK_OTG_PMU 332 203 #define RK3328_HCLK_OTG 333 204 #define RK3328_HCLK_HOST0 334 205 #define RK3328_HCLK_HOST0_ARB 335 206 #define RK3328_HCLK_CRYPTO_MST 336 207 #define RK3328_HCLK_CRYPTO_SLV 337 208 #define RK3328_HCLK_PDM 338 209 #define RK3328_HCLK_IEP 339 210 #define RK3328_HCLK_RGA 340 211 #define RK3328_HCLK_HDCP 341 212 213 #endif /* !_RK3328_CRU_H */ 214
Indexes created Thu Sep 25 16:09:42 GMT 2025