| /src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Checkers/ |
| PointerSubChecker.cpp | 45 const MemRegion *RR = RV.getAsRegion();
47 if (!(LR && RR))
51 const MemRegion *BaseRR = RR->getBaseRegion();
|
| /src/sys/arch/hppa/hppa/ |
| kobj_machdep.c | 95 RR(unsigned int x, unsigned int constant)
176 /* RR(symbol, addend) */
178 value = RR(addr, value);
195 /* RR(symbol - GP, addend) */
197 value = RR(addr - GP, value);
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| RegisterClassInfo.cpp | 74 const BitVector &RR = MF->getRegInfo().getReservedRegs();
75 if (Reserved.size() != RR.size() || RR != Reserved) {
77 Reserved = RR;
|
| RDFLiveness.cpp | 148 RegisterRef RR = TA.Addr->getRegRef(DFG);
150 if (RegisterAggr::isCoverOf(RR, RefRR, PRI))
660 auto ClearIn = [] (RegisterRef RR, const RegisterAggr &Mid, SubMap &SM) {
662 return RR;
663 auto F = SM.find(RR);
666 RegisterRef S = Mid.clearIn(RR);
667 SM.insert({RR, S});
729 RegisterRef RR = NodeAddr<DefNode*>(Ds[0]).Addr->getRegRef(DFG);
730 dbgs() << '<' << Print<RegisterRef>(RR, DFG) << '>';
1130 RegisterRef RR = UA.Addr->getRegRef(DFG)
[all...] |
| RDFGraph.cpp | 418 void RefNode::setRegRef(RegisterRef RR, DataFlowGraph &G) {
421 Ref.PR = G.pack(RR);
596 // For a given instruction, check if there are any bits of RR that can remain
603 // Check if the definition of RR produces an unspecified value.
816 RegisterRef RR, NodeAddr<BlockNode*> PredB, uint16_t Flags) {
819 PUA.Addr->setRegRef(RR, *this);
832 RegisterRef RR, uint16_t Flags) {
835 DA.Addr->setRegRef(RR, *this);
909 RegisterRef RR = *I;
912 NodeAddr<DefNode*> DA = newDef(PA, RR, PhiFlags)
[all...] |
| /src/external/apache2/llvm/dist/llvm/tools/llvm-mca/Views/ |
| BottleneckAnalysis.cpp | 72 const ResourceRef &RR = Use.first;
73 unsigned Index = ProcResID2ResourceUsersIndex[RR.first];
74 Index += countTrailingZeros(RR.second);
|
| ResourcePressureView.cpp | 59 const ResourceRef &RR = Use.first;
60 assert(Resource2VecIndex.find(RR.first) != Resource2VecIndex.end());
61 unsigned R2VIndex = Resource2VecIndex[RR.first];
62 R2VIndex += countTrailingZeros(RR.second);
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/ExecutionEngine/Orc/ |
| OrcRPCTargetProcessControl.h | 313 std::vector<orcrpctpc::RemoteLookupRequest> RR;
315 RR.push_back({});
316 RR.back().first = E.Handle;
318 RR.back().second.push_back(
334 return EP.template callB<orcrpctpc::LookupSymbols>(RR);
|
| /src/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/ |
| ResourceManager.cpp | 194 void ResourceManager::use(const ResourceRef &RR) {
195 // Mark the sub-resource referenced by RR as used.
196 unsigned RSID = getResourceStateIndex(RR.first);
198 RS.markSubResourceAsUsed(RR.second);
202 Strategies[RSID]->used(RR.second);
204 // If there are still available units in RR.first,
209 AvailableProcResUnits ^= RR.first;
211 // Notify groups that RR.first is no longer available.
217 CurrentUser.markSubResourceAsUsed(RR.first);
218 Strategies[GroupIndex]->used(RR.first)
[all...] |
| /src/games/monop/ |
| monop.h | 56 #define RR 1 /* railroad */
146 /*extern RR_S rr[N_RR];*/
|
| /src/external/gpl3/binutils/dist/include/opcode/ |
| spu.h | 30 RR,
|
| /src/external/gpl3/binutils.old/dist/include/opcode/ |
| spu.h | 30 RR,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_stream_encoder.c | 1079 * RR - Rear Right
1096 * RL RR
1109 * 0b00110011 - - RR RL - - FR FL
1110 * 0b00110111 - - RR RL - LFE FR FL
1111 * 0b00111011 - - RR RL FC - FR FL
1112 * 0b00111111 - - RR RL FC LFE FR FL
1113 * 0b01110011 - RC RR RL - - FR FL
1114 * 0b01110111 - RC RR RL - LFE FR FL
1115 * 0b01111011 - RC RR RL FC - FR FL
1116 * 0b01111111 - RC RR RL FC LFE FR F
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_stream_encoder.c | 1038 * RR - Rear Right
1055 * RL RR
1068 * 0b00110011 - - RR RL - - FR FL
1069 * 0b00110111 - - RR RL - LFE FR FL
1070 * 0b00111011 - - RR RL FC - FR FL
1071 * 0b00111111 - - RR RL FC LFE FR FL
1072 * 0b01110011 - RC RR RL - - FR FL
1073 * 0b01110111 - RC RR RL - LFE FR FL
1074 * 0b01111011 - RC RR RL FC - FR FL
1075 * 0b01111111 - RC RR RL FC LFE FR F
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonOptAddrMode.cpp | 170 RegisterRef RR = UA.Addr->getRegRef(*DFG);
171 if (OffsetReg == RR.Reg) {
172 OffsetRR = RR;
292 RegisterRef RR = UA.Addr->getRegRef(*DFG);
293 if (LRExtReg == RR.Reg) {
294 LRExtRR = RR;
|
| HexagonExpandCondsets.cpp | 183 bool operator== (RegisterRef RR) const {
184 return Reg == RR.Reg && Sub == RR.Sub;
186 bool operator!= (RegisterRef RR) const { return !operator==(RR); }
187 bool operator< (RegisterRef RR) const {
188 return Reg < RR.Reg || (Reg == RR.Reg && Sub < RR.Sub);
203 void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec)
[all...] |
| /src/games/sail/ |
| extern.h | 161 char RR; /* 228 */
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/ADT/ |
| ImmutableSet.h | 524 TreeTy *RR = getRight(R);
526 if (getHeight(RR) >= getHeight(RL))
527 return createNode(createNode(L,V,RL), R, RR);
534 return createNode(createNode(L,V,RLL), RL, createNode(RLR,R,RR));
|
| /src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Core/ |
| BugReporterVisitors.cpp | 2093 const MemRegion *RR = getLocationRegionIfReference(Inner, LVNode);
2099 if (RR && !LVIsNull)
2102 *KV, RR, EnableNullFPSuppression, TKind, SFC));
2108 const MemRegion *R = (RR && LVIsNull) ? RR :
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 710 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src);
711 if (RR == 0)
714 ResultReg = RR;
|
| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| CodeGenDAGPatterns.cpp | 4624 Record *RR = DI->getDef();
4625 if (RR->isSubClassOf("Register"))
|
| /src/external/apache2/llvm/dist/clang/lib/Sema/ |
| SemaExpr.cpp | 12994 DeclRefExpr *RR = dyn_cast<DeclRefExpr>(OR->getBase()->IgnoreImpCasts());
12995 if (RL && RR && RL->getDecl() == RR->getDecl())
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 4945 /// Try to make (and/or setcc (LL, LR), setcc (RL, RR)) more efficient.
4948 SDValue LL, LR, RL, RR, N0CC, N1CC;
4950 !isSetCCEquivalent(N1, RL, RR, N1CC))
4956 RL.getValueType() == RR.getValueType() &&
4973 if (LR == RR && CC0 == CC1 && IsInteger) {
5020 ((isNullConstant(LR) && isAllOnesConstant(RR)) ||
5021 (isAllOnesConstant(LR) && isNullConstant(RR)))) {
5037 SDValue XorR = DAG.getNode(ISD::XOR, SDLoc(N1), OpVT, RL, RR);
5048 ConstantSDNode *C1 = isConstOrConstSplat(RR);
5058 SDValue Max = DAG.getNode(ISD::UMAX, DL, OpVT, LR, RR);
[all...] |
