HomeSort by: relevance | last modified time | path
    Searched defs:RS1 (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/arch/sparc/sparc/
db_disasm.c 100 #define RS1(x) (((x) & 0x1f) << 14)
162 1 -- source register operand stored in rs1
165 3 -- floating source register in rs1
174 p -- address computed by the contents of rs1+rs2
175 q -- address computed by the contents of rs1+simm13
177 s -- %asi is implicit in the insn, rs1 value not used
182 7 -- [reg_addr rs1+rs2] imm_asi
183 8 -- [reg_addr rs1+simm13] %asi
188 A -- privileged register encoded in rs1
189 B -- state register encoded in rs1
    [all...]
  /src/sys/arch/sparc64/sparc64/
db_disasm.c 105 #define RS1(x) (((x) & 0x1f) << 14)
167 1 -- source register operand stored in rs1
170 3 -- floating source register in rs1
179 p -- address computed by the contents of rs1+rs2
180 q -- address computed by the contents of rs1+simm13
182 s -- %asi is implicit in the insn, rs1 value not used
187 7 -- [reg_addr rs1+rs2] imm_asi
188 8 -- [reg_addr rs1+simm13] %asi
193 A -- privileged register encoded in rs1
194 B -- state register encoded in rs1
    [all...]
  /src/external/gpl3/gdb/dist/sim/pru/
pru.h 52 #define RS1 extract_regval (CPU.regs[GET_INSN_FIELD (RS1, inst)], \
60 #define XBBO_BASEREG (CPU.regs[GET_INSN_FIELD (RS1, inst)])
  /src/external/gpl3/gdb.old/dist/sim/pru/
pru.h 52 #define RS1 extract_regval (CPU.regs[GET_INSN_FIELD (RS1, inst)], \
60 #define XBBO_BASEREG (CPU.regs[GET_INSN_FIELD (RS1, inst)])
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonSplitDouble.cpp 919 unsigned RS1 = getRegState(Op1);
943 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)
946 .addReg(Op1.getReg(), RS1, HiSR)
950 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)
960 .addReg(Op1.getReg(), RS1, HiSR)
972 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);
974 .addReg(Op1.getReg(), RS1, HiSR)
983 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);
985 .addReg(Op1.getReg(), RS1, HiSR)
  /src/external/gpl3/binutils/dist/include/opcode/
sparc.h 209 1 rs1 register.
232 M alternate space register (asr) in rs1
256 r Single register that is both rs1 and rd.
264 U sparclet coprocessor registers in rs1 position
277 ? Privileged Register in rs1 (v9)
279 $ Hyperprivileged Register in rs1 (v9b)
284 / Ancillary state register in rs1 (v9a)
312 #define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */
322 #define RS1_G0 RS1 (~0
    [all...]
  /src/external/gpl3/binutils.old/dist/include/opcode/
sparc.h 209 1 rs1 register.
232 M alternate space register (asr) in rs1
256 r Single register that is both rs1 and rd.
264 U sparclet coprocessor registers in rs1 position
277 ? Privileged Register in rs1 (v9)
279 $ Hyperprivileged Register in rs1 (v9b)
284 / Ancillary state register in rs1 (v9a)
312 #define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */
322 #define RS1_G0 RS1 (~0
    [all...]
  /src/external/gpl3/gdb/dist/include/opcode/
sparc.h 209 1 rs1 register.
232 M alternate space register (asr) in rs1
256 r Single register that is both rs1 and rd.
264 U sparclet coprocessor registers in rs1 position
277 ? Privileged Register in rs1 (v9)
279 $ Hyperprivileged Register in rs1 (v9b)
284 / Ancillary state register in rs1 (v9a)
312 #define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */
322 #define RS1_G0 RS1 (~0
    [all...]
  /src/external/gpl3/gdb.old/dist/include/opcode/
sparc.h 209 1 rs1 register.
232 M alternate space register (asr) in rs1
256 r Single register that is both rs1 and rd.
264 U sparclet coprocessor registers in rs1 position
277 ? Privileged Register in rs1 (v9)
279 $ Hyperprivileged Register in rs1 (v9b)
284 / Ancillary state register in rs1 (v9a)
312 #define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */
322 #define RS1_G0 RS1 (~0
    [all...]

Completed in 34 milliseconds