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    Searched defs:Reads (Results 1 - 8 of 8) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
MachineInstrBundle.h 219 /// Reads - One of the operands read the virtual register. This does not
221 bool Reads;
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenSchedule.h 70 // added. Note that implicit Reads (from ReadVariant) may have a Sequence
118 /// provided InstrRW records for this class. ItinClassDef or Writes/Reads may
126 /// that mapped the itinerary class to the variant Writes or Reads.
133 IdxVec Reads;
153 makeArrayRef(Reads) == R;
562 void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
638 void collectRWResources(ArrayRef<unsigned> Writes, ArrayRef<unsigned> Reads,
SubtargetEmitter.cpp 1024 IdxVec Reads = SC.Reads;
1038 Reads.clear();
1040 Writes, Reads);
1049 Writes, Reads);
1149 for (unsigned UseIdx = 0, EndIdx = Reads.size();
1152 FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel);
CodeGenSchedule.cpp 567 // Reads don't currently have sequence records, but it can be added later.
588 // Reserve idx=0 for invalid writes/reads.
658 // itinerary resources. Index reads and writes in separate domains.
687 dbgs() << "\n+++ SCHED READS and WRITES (collectSchedRW) +++\n";
756 IdxVec &Writes, IdxVec &Reads) const {
761 findRWs(ReadDefs, Reads, true);
874 IdxVec Writes, Reads;
876 findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads);
879 unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, /*ProcIndices*/{0});
926 for (unsigned int Read : SC.Reads)
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  /src/external/apache2/llvm/dist/llvm/include/llvm/MCA/
Instruction.h 10 /// This file defines abstractions used by the Pipeline to model register reads,
67 // reads. Implicit reads have negative indices. The actual operand index of an
141 // A list of dependent reads. Users is a set of dependent
142 // reads. A dependent read is added to the set only if CyclesLeft
171 // This method adds Use to the set of data dependent reads. IID is the
350 SmallVector<ReadDescriptor, 4> Reads; // Implicit reads are at the end.
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
EarlyIfConversion.cpp 368 SmallVector<MCRegister, 8> Reads;
393 // Unless I reads Reg.
395 Reads.push_back(Reg.asMCReg());
398 while (!Reads.empty())
399 for (MCRegUnitIterator Units(Reads.pop_back_val(), TRI); Units.isValid();
MachinePipeliner.cpp 2561 bool Reads, Writes;
2562 std::tie(Reads, Writes) =
2564 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) {
2568 } else if (MO.isDef() && Reads && stageScheduled(*I) > StageInst1) {
RegisterCoalescer.cpp 302 /// If the given machine operand reads only undefined lanes add an undef
1751 bool Reads, Writes;
1752 std::tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
1756 if (DstInt && !Reads && SubIdx && !UseMI->isDebugValue())
1757 Reads = DstInt->liveAt(LIS->getInstructionIndex(*UseMI));
1767 MO.setIsUndef(!Reads);
3012 // No need to check the instruction defining VNI for reads.

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