| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIProgramInfo.cpp | 35 uint64_t Reg = S_00B848_VGPRS(VGPRBlocks) | S_00B848_SGPRS(SGPRBlocks) |
41 Reg |= S_00B028_MEM_ORDERED(MemOrdered);
44 Reg |= S_00B128_MEM_ORDERED(MemOrdered);
47 Reg |= S_00B228_WGP_MODE(WgpMode) | S_00B228_MEM_ORDERED(MemOrdered);
50 Reg |= S_00B428_WGP_MODE(WgpMode) | S_00B428_MEM_ORDERED(MemOrdered);
55 return Reg;
|
| GCNRegPressure.cpp | 30 const unsigned Reg = Register::index2VirtReg(I);
31 if (!LIS.hasInterval(Reg))
33 const auto &LI = LIS.getInterval(Reg);
39 dbgs() << " " << printReg(Reg, MRI.getTargetRegisterInfo())
72 unsigned GCNRegPressure::getRegKind(Register Reg,
74 assert(Reg.isVirtual());
75 const auto RC = MRI.getRegClass(Reg);
84 void GCNRegPressure::inc(unsigned Reg,
98 switch (auto Kind = getRegKind(Reg, MRI)) {
115 Value[Kind] += Sign * MRI.getPressureSets(Reg).getWeight()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreFrameToArgsOffsetElim.cpp | 58 Register Reg = OldInst.getOperand(0).getReg();
59 MBBI = TII.loadImmediate(MBB, MBBI, Reg, StackSize);
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| Register.h | 20 unsigned Reg;
23 constexpr Register(unsigned Val = 0): Reg(Val) {}
24 constexpr Register(MCRegister Val): Reg(Val) {}
36 static_assert(std::numeric_limits<decltype(Reg)>::max() >= 0xFFFFFFFF,
37 "Reg isn't large enough to hold full range.");
41 /// returns true if Reg is in the range used for stack slots.
44 static bool isStackSlot(unsigned Reg) {
45 return MCRegister::isStackSlot(Reg);
49 bool isStack() const { return MCRegister::isStackSlot(Reg); }
52 static int stackSlot2Index(Register Reg) {
[all...] |
| LiveRegUnits.h | 56 Register Reg = O->getReg();
57 if (!Reg.isPhysical())
63 if (!TRI->isConstantPhysReg(Reg))
64 ModifiedRegUnits.addReg(Reg);
66 assert(O->isUse() && "Reg operand not a def and not a use");
67 UsedRegUnits.addReg(Reg);
85 /// Adds register units covered by physical register \p Reg.
86 void addReg(MCPhysReg Reg) {
87 for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit)
91 /// Adds register units covered by physical register \p Reg that ar
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| CalcSpillWeights.cpp | 38 unsigned Reg = Register::index2VirtReg(I);
39 if (MRI.reg_nodbg_empty(Reg))
41 calculateSpillWeightAndHint(LIS.getInterval(Reg));
45 // Return the preferred allocation register for reg, given a COPY instruction.
46 static Register copyHint(const MachineInstr *MI, unsigned Reg,
51 if (MI->getOperand(0).getReg() == Reg) {
67 const TargetRegisterClass *rc = MRI.getRegClass(Reg);
72 // Check if reg:sub matches so that a super register could be hinted.
83 unsigned Reg = LI.reg();
[all...] |
| DeadMachineInstructionElim.cpp | 82 Register Reg = MO.getReg();
83 if (Register::isPhysicalRegister(Reg)) {
85 if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg))
92 for (auto &U : MRI->use_nodbg_operands(Reg))
97 for (const MachineInstr &Use : MRI->use_nodbg_instructions(Reg)) {
162 Register Reg = MO.getReg();
163 if (Register::isPhysicalRegister(Reg)) {
167 for (MCSubRegIterator SR(Reg, TRI,/*IncludeSelf=*/true);
181 Register Reg = MO.getReg()
[all...] |
| MIRVRegNamerUtils.h | 36 Register Reg;
40 NamedVReg(Register Reg, std::string Name = "") : Reg(Reg), Name(Name) {}
41 NamedVReg(std::string Name = "") : Reg(~0U), Name(Name) {}
45 Register getReg() const { return Reg; }
|
| RegAllocBase.cpp | 75 Register Reg = Register::index2VirtReg(i);
76 if (MRI->reg_nodbg_empty(Reg))
78 enqueue(&LIS->getInterval(Reg));
89 assert(!VRM->hasPhys(VirtReg->reg()) && "Register already assigned");
92 if (MRI->reg_nodbg_empty(VirtReg->reg())) {
95 LIS->removeInterval(VirtReg->reg());
106 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg()))
119 I = MRI->reg_instr_begin(VirtReg->reg()),
127 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg->reg());
142 VRM->assignVirt2Phys(VirtReg->reg(), AllocOrder.front())
[all...] |
| TargetFrameLoweringImpl.cpp | 123 unsigned Reg = CSRegs[i];
124 if (CallsUnwindInit || MRI.isPhysRegModified(Reg))
125 SavedRegs.set(Reg);
|
| TargetRegisterInfo.cpp | 42 #define DEBUG_TYPE "target-reg-info"
72 MachineInstr *MI = MRI.getUniqueVRegDef(VirtReg.reg());
80 MCRegister Reg) const {
81 for (MCSuperRegIterator AI(Reg, this, true); AI.isValid(); ++AI)
89 for (unsigned Reg : RegisterSet.set_bits()) {
90 if (Checked[Reg])
92 for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) {
93 if (!RegisterSet[*SR] && !is_contained(Exceptions, Reg)) {
95 << " of reserved register " << printReg(Reg, this)
110 Printable printReg(Register Reg, const TargetRegisterInfo *TRI
[all...] |
| ProcessImplicitDefs.cpp | 77 Register Reg = MI->getOperand(0).getReg();
79 if (Register::isVirtualRegister(Reg)) {
82 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
106 !TRI->regsOverlap(Reg, UserReg))
108 // UserMI uses or redefines Reg. Set <undef> flags on all uses.
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMInstrInfo.cpp | 122 Register Reg = MI->getOperand(0).getReg();
125 MIB = BuildMI(MBB, MI, DL, get(ARM::MOV_ga_pcrel_ldr), Reg)
133 BuildMI(MBB, MI, DL, get(ARM::LDRi12), Reg)
134 .addReg(Reg, RegState::Kill)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/CSKY/MCTargetDesc/ |
| CSKYMCTargetDesc.cpp | 41 unsigned Reg = MRI.getDwarfRegNum(CSKY::R14, true);
42 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kCallingConv.h | 64 unsigned Reg =
67 if (Reg) {
68 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
|
| M68kFrameLowering.cpp | 160 unsigned Reg = MO.getReg();
161 if (!Reg)
163 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
176 static bool isRegLiveIn(MachineBasicBlock &MBB, unsigned Reg) {
178 [Reg](MachineBasicBlock::RegisterMaskPair RegMask) {
179 return RegMask.PhysReg == Reg;
199 const DebugLoc &DL, unsigned Reg,
211 .addReg(Reg)
222 BuildMI(MBB, MBBI, DL, TII.get(MovOp), Reg)
350 Register Reg;
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCCallingConv.cpp | 118 unsigned Reg = State.AllocateReg(HiRegList);
119 if (!Reg)
124 if (HiRegList[i] == Reg)
131 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
147 unsigned Reg = State.AllocateReg(HiRegList, LoRegList);
148 if (!Reg)
153 if (HiRegList[i] == Reg)
156 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
|
| PPCRegisterInfo.h | 27 unsigned Reg = 0;
30 Reg = PPC::CR0;
33 Reg = PPC::CR1;
36 Reg = PPC::CR2;
39 Reg = PPC::CR3;
42 Reg = PPC::CR4;
45 Reg = PPC::CR5;
48 Reg = PPC::CR6;
51 Reg = PPC::CR7;
53 assert(Reg != 0 && "Invalid CR bit register")
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/MCTargetDesc/ |
| SparcMCTargetDesc.cpp | 39 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true);
40 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0);
49 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true);
50 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 2047);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/MCTargetDesc/ |
| VEMCTargetDesc.cpp | 38 unsigned Reg = MRI.getDwarfRegNum(VE::SX11, true);
39 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyOptimizeLiveIntervals.cpp | 85 unsigned Reg = Register::index2VirtReg(I);
88 if (MRI.reg_nodbg_empty(Reg))
91 LIS.splitSeparateComponents(LIS.getInterval(Reg), SplitLIs);
92 if (Reg == TRI.getFrameRegister(MF) && SplitLIs.size() > 0) {
100 SplitLIs.back()->reg());
|
| WebAssemblyPrepareForLiveIntervals.cpp | 65 static bool hasArgumentDef(unsigned Reg, const MachineRegisterInfo &MRI) {
66 for (const auto &Def : MRI.def_instructions(Reg))
98 unsigned Reg = Register::index2VirtReg(I);
101 if (MRI.use_nodbg_empty(Reg))
105 if (hasArgumentDef(Reg, MRI))
109 TII.get(WebAssembly::IMPLICIT_DEF), Reg);
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| Utils.h | 81 /// Try to constrain Reg to the specified register class. If this fails,
87 const RegisterBankInfo &RBI, Register Reg,
107 /// Try to constrain Reg so that it is usable by argument OpIdx of the provided
198 /// See if Reg is defined by an single def instruction that is
201 MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg,
208 Register Reg;
211 /// Find the def instruction for \p Reg, and underlying value Register folding
216 getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI);
218 /// Find the def instruction for \p Reg, folding away any trivial copies. May
219 /// return nullptr if \p Reg is not a generic virtual register
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64DeadRegisterDefinitionsPass.cpp | 1 //==-- AArch64DeadRegisterDefinitions.cpp - Replace dead defs w/ zero reg --==//
148 Register Reg = MO.getReg();
149 if (!Register::isVirtualRegister(Reg) ||
150 (!MO.isDead() && !MRI->use_nodbg_empty(Reg)))
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsELFStreamer.cpp | 49 unsigned Reg = Op.getReg();
50 RegInfoRecord->SetPhysRegUsed(Reg, MCRegInfo);
|
