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    Searched defs:Reg1 (Results 1 - 22 of 22) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelDAGToDAG.cpp 225 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg();
249 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
264 SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32,
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/
AArch64AsmBackend.cpp 625 unsigned Reg1 = *MRI.getLLVMRegNum(Inst.getRegister(), true);
650 Reg1 = getXRegFromWReg(Reg1);
653 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 &&
656 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 &&
659 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 &&
662 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 &&
665 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 &&
669 Reg1 = getDRegFromBReg(Reg1);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/
MipsMCCodeEmitter.cpp 99 unsigned Reg1 = Ctx.getRegisterInfo()->getEncodingValue(RegOp1);
103 assert(Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!");
104 if (Reg0 < Reg1)
107 if (Reg0 >= Reg1)
111 if (Reg1 >= Reg0)
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCVSXSwapRemoval.cpp 896 Register Reg1 = MI->getOperand(1).getReg();
899 MI->getOperand(2).setReg(Reg1);
PPCRegisterInfo.cpp 801 Register Reg1 = Reg;
806 .addReg(Reg1, RegState::Kill)
846 Register Reg1 = Reg;
852 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
960 Register Reg1 = Reg;
965 .addReg(Reg1, RegState::Kill)
PPCInstrInfo.cpp 1170 Register Reg1 = MI.getOperand(1).getReg();
1179 if (Reg0 == Reg1) {
1204 .addReg(Reg1, getKillRegState(Reg1IsKill))
1213 MI.getOperand(2).setReg(Reg1);
3613 // Imm instr1: Reg1 = op1 OffsetImm, ToBeDeletedReg1(killed)
3621 // Index instr1: Reg1 = opx1 ScaleReg1, ToBeChangedReg
  /src/external/apache2/llvm/dist/llvm/include/llvm/MC/
MCRegisterInfo.h 78 bool contains(MCRegister Reg1, MCRegister Reg2) const {
79 return contains(Reg1) && contains(Reg2);
748 uint16_t Reg1 = 0;
756 Reg1 = MCRI->RegUnitRoots[RegUnit][1];
772 Reg0 = Reg1;
773 Reg1 = 0;
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
Thumb2SizeReduction.cpp 757 Register Reg1 = MI->getOperand(1).getReg();
762 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1)
768 if (Reg1 != Reg0)
775 } else if (Reg0 != Reg1) {
ARMFastISel.cpp 2789 unsigned Reg1 = getRegForValue(Src1Value);
2790 if (Reg1 == 0) return false;
2803 .addReg(Reg1);
ARMBaseInstrInfo.cpp 1640 [&TRI](const unsigned &Reg1, const unsigned &Reg2) -> bool {
1641 return TRI.getEncodingValue(Reg1) <
3395 Register Reg1 = UseMI.getOperand(OpIdx).getReg();
3401 .addReg(Reg1, getKillRegState(isKill))
ARMISelDAGToDAG.cpp 5530 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg();
5554 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
5569 SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32,
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsSEFrameLowering.cpp 465 unsigned Reg1 =
469 std::swap(Reg0, Reg1);
477 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
482 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1;
485 std::swap(Reg0, Reg1);
493 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86AvoidStoreForwardingBlocks.cpp 396 Register Reg1 = MRI->createVirtualRegister(
400 Reg1)
425 .addReg(Reg1)
X86ExpandPseudo.cpp 468 Register Reg1 = TRI->getSubReg(Reg, X86::sub_mask_1);
473 .addReg(Reg1, RegState::Define | getDeadRegState(DstIsDead));
502 Register Reg1 = TRI->getSubReg(Reg, X86::sub_mask_1);
515 MIBHi.addReg(Reg1, getKillRegState(SrcIsKill));
X86InstrInfo.cpp 5633 Register Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
5642 if ((HasDef && Reg0 == Reg1 && Tied1) ||
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetInstrInfo.cpp 185 Register Reg1 = MI.getOperand(Idx1).getReg();
198 bool Reg1IsRenamable = Register::isPhysicalRegister(Reg1)
206 if (HasDef && Reg0 == Reg1 &&
214 Reg0 = Reg1;
231 CommutedMI->getOperand(Idx2).setReg(Reg1);
243 if (Register::isPhysicalRegister(Reg1))
RegisterCoalescer.cpp 2612 Register Reg1;
2613 std::tie(Orig1, Reg1) = Other.followCopyChain(Value1);
2618 return Orig0 == Orig1 && Reg0 == Reg1;
2624 return Orig0->def == Orig1->def && Reg0 == Reg1;
  /src/external/apache2/llvm/dist/llvm/lib/MC/
MCDwarf.cpp 1347 unsigned Reg1 = Instr.getRegister();
1350 Reg1 = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg1);
1354 Streamer.emitULEB128IntValue(Reg1);
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/AsmParser/
SystemZAsmParser.cpp 417 bool parseAddress(bool &HaveReg1, Register &Reg1, bool &HaveReg2,
988 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
989 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
1017 // The restriction only applies to the first Register (i.e. Reg1). Reg2 is
1018 // always a general register. Reg1 should be of group RegV if "HasVectorIndex"
1028 if (parseRegister(Reg1))
1047 if (parseIntegerRegister(Reg1, RegGroup))
1101 Register Reg1, Reg2;
1108 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength,
1121 // If we have Reg1, it must be an address register
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64FrameLowering.cpp 760 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg());
763 .addImm(Reg1)
773 Register Reg1 = MBBI->getOperand(2).getReg();
774 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR)
781 .addImm(RegInfo->getSEHRegNum(Reg1))
811 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());
814 .addImm(Reg1)
822 Register Reg1 = MBBI->getOperand(1).getReg();
823 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR)
830 .addImm(RegInfo->getSEHRegNum(Reg1))
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonConstPropagation.cpp 868 // reg0 = PHI reg1, bb2, reg3, bb4, ...
2608 bool Reg1 = Src1.isReg(), Reg2 = Src2.isReg();
2610 if (Reg1) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp 7413 unsigned Reg1 = Op1.getReg();
7415 unsigned Rt = MRI->getEncodingValue(Reg1);
7425 Reg1, ARM::gsub_0, &(MRI->getRegClass(ARM::GPRPairRegClassID)));

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