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    Searched defs:RegA (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86WinAllocaExpander.cpp 220 unsigned RegA = Is64Bit ? X86::RAX : X86::EAX;
222 .addReg(RegA, RegState::Undef);
234 unsigned RegA = Is64Bit ? X86::RAX : X86::EAX;
236 .addReg(RegA, RegState::Undef);
248 unsigned RegA = Is64BitAlloca ? X86::RAX : X86::EAX;
249 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::COPY), RegA)
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
ImplicitNullChecks.cpp 288 Register RegA = MOA.getReg();
295 if (TRI->regsOverlap(RegA, RegB) && (MOA.isDef() || MOB.isDef()))
TwoAddressInstructionPass.cpp 125 bool isProfitableToCommute(Register RegA, Register RegB, Register RegC,
131 bool isProfitableToConv3Addr(Register RegA, Register RegB);
134 MachineBasicBlock::iterator &nmi, Register RegA,
416 static bool regsAreCompatible(Register RegA, Register RegB,
418 if (RegA == RegB)
420 if (!RegA || !RegB)
422 return TRI->regsOverlap(RegA, RegB);
437 bool TwoAddressInstructionPass::isProfitableToCommute(Register RegA,
476 MCRegister ToRegA = getMappedReg(RegA, DstRegMap);
484 // -RegB is not tied to a register and RegC is compatible with RegA
    [all...]
TargetInstrInfo.cpp 844 Register RegA = OpA.getReg();
850 if (Register::isVirtualRegister(RegA))
851 MRI.constrainRegClass(RegA, RC);
879 .addReg(RegA, getKillRegState(KillA))
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 527 Register RegA = Prev->getOperand(AddOpIdx).getReg();
528 MachineInstr *Leaf = MRI->getUniqueVRegDef(RegA);

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