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    Searched defs:RegClass (Results 1 - 23 of 23) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/
RegisterAliasing.cpp 33 const MCRegisterClass &RegClass)
35 for (MCPhysReg PhysReg : RegClass)
76 const auto &RegClass = RegInfo.getRegClass(RegClassIndex);
78 Found.reset(new RegisterAliasingTracker(RegInfo, ReservedReg, RegClass));
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyPeephole.cpp 97 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
98 switch (RegClass->getID()) {
123 Register NewReg = MRI.createVirtualRegister(RegClass);
WebAssemblyRegStackify.cpp 106 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg());
107 if (RegClass == &WebAssembly::I32RegClass) {
110 } else if (RegClass == &WebAssembly::I64RegClass) {
113 } else if (RegClass == &WebAssembly::F32RegClass) {
118 } else if (RegClass == &WebAssembly::F64RegClass) {
123 } else if (RegClass == &WebAssembly::V128RegClass) {
639 const auto *RegClass = MRI.getRegClass(Reg);
640 Register TeeReg = MRI.createVirtualRegister(RegClass);
641 Register DefReg = MRI.createVirtualRegister(RegClass);
644 TII->get(getTeeOpcode(RegClass)), TeeReg
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
RegisterClassInfo.h 47 std::unique_ptr<RCInfo[]> RegClass;
77 const RCInfo &RCI = RegClass[RC->getID()];
RDFRegisters.h 143 const TargetRegisterClass *RegClass = nullptr;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
RenameIndependentSubregs.cpp 134 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
142 Register NewVReg = MRI->createVirtualRegister(RegClass);
LiveIntervals.cpp 1741 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
1743 Register NewVReg = MRI->createVirtualRegister(RegClass);
TargetInstrInfo.cpp 53 short RegClass = MCID.OpInfo[OpNum].RegClass;
55 return TRI->getPointerRegClass(MF, RegClass);
58 if (RegClass < 0)
62 return TRI->getRegClass(RegClass);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
Utils.cpp 41 const TargetRegisterClass &RegClass) {
42 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI))
43 return MRI.createVirtualRegister(&RegClass);
52 const TargetRegisterClass &RegClass, MachineOperand &RegMO) {
57 Register ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass);
102 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF);
111 if (RegClass && !RegClass->isAllocatable())
112 RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI);
114 if (!RegClass) {
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMBaseRegisterInfo.cpp 832 const TargetRegisterClass *RegClass =
836 (Register::isVirtualRegister(FrameReg) || RegClass->contains(FrameReg)))
840 ScratchReg = MF.getRegInfo().createVirtualRegister(RegClass);
MVETPAndVPTOptimisationsPass.cpp 579 const TargetRegisterClass *RegClass = RegInfo.getRegClassOrNull(DstReg);
580 return RegClass && (RegClass->getID() == ARM::VCCRRegClassID);
ARMFrameLowering.cpp 1643 const TargetRegisterClass *RegClass = TII.getRegClass(MCID, i, TRI, MF);
1644 if (RegClass && !RegClass->contains(ARM::SP))
ARMBaseInstrInfo.cpp 1524 llvm_unreachable("Unknown regclass!");
2531 const TargetRegisterClass *RegClass;
2534 RegClass = &ARM::DPRRegClass;
2537 RegClass = &ARM::GPRRegClass;
2564 unsigned CurReg = RegClass->getRegister(CurRegEnc);
ARMISelDAGToDAG.cpp 1831 SDValue RegClass =
1835 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1842 SDValue RegClass =
1846 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1853 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl,
1857 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1864 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl,
1868 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1876 SDValue RegClass =
1882 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1
    [all...]
ARMISelLowering.cpp 9761 SDValue RegClass =
9765 const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 };
  /src/external/apache2/llvm/dist/llvm/include/llvm/MC/
MCInstrDesc.h 89 int16_t RegClass;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64AsmPrinter.cpp 756 const TargetRegisterClass *RegClass;
758 RegClass = &AArch64::ZPRRegClass;
760 RegClass = &AArch64::PPRRegClass;
762 RegClass = &AArch64::FPR128RegClass;
767 return printAsmRegInClass(MO, RegClass, AltName, O);
AArch64ISelLowering.cpp 7929 // only take 128-bit registers so just use that regclass.
16609 SDValue RegClass =
16613 const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 };
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
FastISel.cpp 1902 const TargetRegisterClass *RegClass =
1904 if (!MRI.constrainRegClass(Op, RegClass)) {
1907 Register NewOp = createResultReg(RegClass);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUISelDAGToDAG.cpp 577 int RegClass = Desc.OpInfo[OpIdx].RegClass;
578 if (RegClass == -1)
581 return Subtarget->getRegisterInfo()->getRegClass(RegClass);
652 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
656 RegClass);
SIInstrInfo.cpp 988 const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg);
989 if (RegClass == &AMDGPU::SReg_32RegClass ||
990 RegClass == &AMDGPU::SGPR_32RegClass ||
991 RegClass == &AMDGPU::SReg_32_XM0RegClass ||
992 RegClass == &AMDGPU::SReg_32_XM0_XEXECRegClass) {
998 if (RegClass == &AMDGPU::SReg_64RegClass ||
999 RegClass == &AMDGPU::SGPR_64RegClass ||
1000 RegClass == &AMDGPU::SReg_64_XEXECRegClass) {
1006 if (RegClass == &AMDGPU::VGPR_32RegClass) {
1011 if (RegClass->hasSuperClassEq(&AMDGPU::VReg_64RegClass))
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelDAGToDAG.cpp 4475 unsigned RegClass = TLI->getRegClassFor(MaskVT)->getID();
4476 SDValue RC = CurDAG->getTargetConstant(RegClass, dl, MVT::i32);
4513 unsigned RegClass = TLI->getRegClassFor(ResVT)->getID();
4514 SDValue RC = CurDAG->getTargetConstant(RegClass, dl, MVT::i32);
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 6991 const TargetRegisterClass *RegClass =
6994 auto HandleRegLoc = [&, RegClass, LocVT](const MCPhysReg PhysReg,
6996 const unsigned VReg = MF.addLiveIn(PhysReg, RegClass);
12489 "Unsupported RegClass.");
12497 "Unsupported RegClass.");
12521 // so we have done the RegClass conversion from RegClass::SrcReg to
12522 // RegClass::DestReg.
12553 // subregisters, we only care about its RegClass, so we should use an

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