HomeSort by: relevance | last modified time | path
    Searched defs:RegClassID (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64A57FPLoadBalancing.cpp 518 unsigned RegClassID = ChainBegin->getDesc().OpInfo[0].RegClass;
519 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID));
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/AsmParser/
RISCVAsmParser.cpp 906 unsigned RegClassID;
908 RegClassID = RISCV::VRM2RegClassID;
910 RegClassID = RISCV::VRM4RegClassID;
912 RegClassID = RISCV::VRM8RegClassID;
916 &RISCVMCRegisterClasses[RegClassID]);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUISelDAGToDAG.cpp 137 void SelectBuildVector(SDNode *N, unsigned RegClassID);
647 void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) {
652 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
669 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
774 unsigned RegClassID =
776 SelectBuildVector(N, RegClassID);
3081 unsigned RegClassID;
3087 case 2: RegClassID = R600::R600_Reg64RegClassID; break;
3090 RegClassID = R600::R600_Reg128VerticalRegClassID;
3092 RegClassID = R600::R600_Reg128RegClassID
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/AsmParser/
X86AsmParser.cpp 1085 unsigned GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, bool IsSIReg);
1143 bool parseSEHRegisterNumber(unsigned RegClassID, unsigned &RegNo);
1611 unsigned X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, unsigned Reg,
1613 switch (RegClassID) {
1647 int RegClassID = -1;
1668 if (RegClassID != -1 &&
1669 !X86MCRegisterClasses[RegClassID].contains(OrigReg)) {
1675 RegClassID = X86::GR64RegClassID;
1677 RegClassID = X86::GR32RegClassID;
1679 RegClassID = X86::GR16RegClassID
    [all...]

Completed in 21 milliseconds