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    Searched defs:RegClassInfo (Results 1 - 15 of 15) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
CriticalAntiDepBreaker.h 41 const RegisterClassInfo &RegClassInfo;
RegAllocBase.h 69 RegisterClassInfo RegClassInfo;
AggressiveAntiDepBreaker.h 122 const RegisterClassInfo &RegClassInfo;
BreakFalseDeps.cpp 38 RegisterClassInfo RegClassInfo;
153 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC);
286 RegClassInfo.runOnMachineFunction(mf);
MachineCombiner.cpp 76 RegisterClassInfo RegClassInfo;
561 TII->shouldReduceRegisterPressure(MBB, &RegClassInfo);
722 RegClassInfo.runOnMachineFunction(MF);
PostRASchedulerList.cpp 80 RegisterClassInfo RegClassInfo;
289 RegClassInfo.runOnMachineFunction(Fn);
312 SchedulePostRATDList Scheduler(Fn, MLI, AA, RegClassInfo, AntiDepMode,
MachineSink.cpp 124 RegisterClassInfo RegClassInfo;
430 RegClassInfo.runOnMachineFunction(MF);
714 RPTracker.init(MBB.getParent(), &RegClassInfo, nullptr, &MBB, MBB.end(),
RegAllocFast.cpp 79 RegisterClassInfo RegClassInfo;
777 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC);
830 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC);
961 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC);
1195 unsigned ClassSize0 = RegClassInfo.getOrder(&RC0).size();
1196 unsigned ClassSize1 = RegClassInfo.getOrder(&RC1).size();
1523 RegClassInfo.runOnMachineFunction(MF);
RegisterCoalescer.cpp 134 RegisterClassInfo RegClassInfo;
2056 if (!CP.isPhys() && RegClassInfo.isProperSubClass(CP.getNewRC()))
4022 RegClassInfo.runOnMachineFunction(fn);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIPreAllocateWWMRegs.cpp 38 RegisterClassInfo RegClassInfo;
103 for (MCRegister PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) {
211 RegClassInfo.runOnMachineFunction(MF);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
TargetRegisterInfo.h 235 struct RegClassInfo {
247 const RegClassInfo *const RCInfos;
257 const RegClassInfo *const RCIs,
719 const RegClassInfo &getRegClassInfo(const TargetRegisterClass &RC) const {
MachinePipeliner.h 68 RegisterClassInfo RegClassInfo;
116 const RegisterClassInfo &RegClassInfo;
197 RegClassInfo(rci), II_setByPragma(II), Topo(SUnits, &ExitSU) {
MachineScheduler.h 128 RegisterClassInfo *RegClassInfo;
387 RegisterClassInfo *RegClassInfo;
431 RegClassInfo(C->RegClassInfo), RPTracker(RegPressure),
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/MIRParser/
MIParser.cpp 306 auto RegClassInfo = Names2RegClasses.find(Name);
307 if (RegClassInfo == Names2RegClasses.end())
309 return RegClassInfo->getValue();
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMLoadStoreOptimizer.cpp 111 RegisterClassInfo RegClassInfo;
585 RegClassInfo.runOnMachineFunction(*MF);
589 for (unsigned Reg : RegClassInfo.getOrder(&RegClass))

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