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    Searched defs:RegIdx (Results 1 - 14 of 14) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRAsmPrinter.cpp 118 unsigned RegIdx = ByteNumber / BytesPerReg;
119 assert(RegIdx < NumOpRegs && "Multibyte index out of range.");
121 Reg = MI->getOperand(OpNum + RegIdx).getReg();
AVRISelLowering.cpp 1040 unsigned RegIdx = RegLastIdx + TotalBytes;
1041 RegLastIdx = RegIdx;
1043 if (RegIdx >= array_lengthof(RegList8)) {
1058 Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
1060 Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
1069 RegIdx -= VT.getStoreSize();
1106 int RegIdx = TotalBytes - 1;
1111 Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
1113 Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
1120 RegIdx -= VT.getStoreSize()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMCallingConv.cpp 201 unsigned RegIdx = State.getFirstUnallocated(RegList);
206 while (RegIdx % RegAlign != 0 && RegIdx < RegList.size())
207 State.AllocateReg(RegList[RegIdx++]);
248 unsigned RegIdx = State.getFirstUnallocated(RegList);
250 if (RegIdx >= RegList.size())
253 It.convertToReg(State.AllocateReg(RegList[RegIdx++]));
ARMISelLowering.cpp 4300 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
4301 if (RegIdx != array_lengthof(GPRArgRegs))
4302 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64CollectLOH.cpp 553 int RegIdx = mapRegToGPRIndex(LI.PhysReg);
554 if (RegIdx >= 0)
555 LOHInfos[RegIdx].OneUser = true;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
DetectDeadLanes.cpp 109 void PutInWorklist(unsigned RegIdx) {
110 if (WorklistMembers.test(RegIdx))
112 WorklistMembers.set(RegIdx);
113 Worklist.push_back(RegIdx);
360 unsigned RegIdx = Register::virtReg2Index(Reg);
361 DefinedByCopy.set(RegIdx);
362 PutInWorklist(RegIdx);
493 for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) {
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsSEISelDAGToDAG.cpp 78 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
79 uint64_t RegNum = cast<ConstantSDNode>(RegIdx)->getZExtValue();
844 SDValue RegIdx = Node->getOperand(2);
846 getMSACtrlReg(RegIdx), MVT::i32);
914 SDValue RegIdx = Node->getOperand(2);
917 getMSACtrlReg(RegIdx), Value);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86SpeculativeLoadHardening.cpp 1874 unsigned RegIdx = Log2_32(RegBytes);
1875 assert(RegIdx < 4 && "Unsupported register size");
1887 if (RC == NOREXRegClasses[RegIdx])
1893 return RC->hasSuperClassEq(GPRRegClasses[RegIdx]);
X86FastISel.cpp 2636 unsigned RegIdx = X86::sub_16bit;
2637 ResultReg = fastEmitInst_extractsubreg(MVT::i16, ResultReg, RegIdx);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/
AMDGPUAsmParser.cpp 2452 unsigned RegIdx = RegNum / AlignSize;
2461 if (RegIdx >= RC.getNumRegs()) {
2466 return RC.getRegister(RegIdx);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIISelLowering.cpp 1880 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgVGPRs);
1881 if (RegIdx == ArgVGPRs.size()) {
1888 unsigned Reg = ArgVGPRs[RegIdx];
1902 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgSGPRs);
1903 if (RegIdx == ArgSGPRs.size())
1906 unsigned Reg = ArgSGPRs[RegIdx];
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp 6848 unsigned RegIdx = 3;
6856 RegIdx = 4;
6858 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() &&
6860 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) ||
6862 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/
MipsAsmParser.cpp 879 struct RegIdxOp RegIdx;
894 Op->RegIdx.Index = Index;
895 Op->RegIdx.RegInfo = RegInfo;
896 Op->RegIdx.Kind = RegKind;
897 Op->RegIdx.Tok.Data = Str.data();
898 Op->RegIdx.Tok.Length = Str.size();
908 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
909 AsmParser.warnIfRegIndexIsAT(RegIdx.Index, StartLoc);
911 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 6739 unsigned RegIdx = State.getFirstUnallocated(ArgGPRs);
6741 if (RegIdx != array_lengthof(ArgGPRs) && RegIdx % 2 == 1)

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