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    Searched defs:RegOp (Results 1 - 25 of 26) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/MCTargetDesc/
BPFInstPrinter.cpp 67 const MCOperand &RegOp = MI->getOperand(OpNo);
71 assert(RegOp.isReg() && "Register operand not a register");
72 O << getRegisterName(RegOp.getReg());
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRAsmPrinter.cpp 99 const MachineOperand &RegOp = MI->getOperand(OpNum);
101 assert(RegOp.isReg() && "Operand must be a register when you're"
103 Register Reg = RegOp.getReg();
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiAsmPrinter.cpp 130 unsigned RegOp = OpNo + 1;
131 if (RegOp >= MI->getNumOperands())
133 const MachineOperand &MO = MI->getOperand(RegOp);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/MCTargetDesc/
AVRMCCodeEmitter.cpp 137 auto RegOp = MI.getOperand(OpNo);
140 assert(RegOp.isReg() && "Expected register operand");
144 switch (RegOp.getReg()) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/MCTargetDesc/
LanaiInstPrinter.cpp 214 const MCOperand &RegOp) {
215 assert(RegOp.isReg() && "Register operand expected");
219 OS << "%" << LanaiInstPrinter::getRegisterName(RegOp.getReg());
240 const MCOperand &RegOp = MI->getOperand(OpNo);
249 printMemoryBaseRegister(OS, AluCode, RegOp);
255 const MCOperand &RegOp = MI->getOperand(OpNo);
259 assert(OffsetOp.isReg() && RegOp.isReg() && "Registers expected.");
265 OS << "%" << getRegisterName(RegOp.getReg());
276 const MCOperand &RegOp = MI->getOperand(OpNo);
285 printMemoryBaseRegister(OS, AluCode, RegOp);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMAsmPrinter.cpp 398 unsigned RegOp = FirstHalf ? OpNum : OpNum + 1;
399 if (RegOp >= MI->getNumOperands())
401 const MachineOperand &MO = MI->getOperand(RegOp);
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/AsmParser/
BPFAsmParser.cpp 89 struct RegOp {
100 RegOp Reg;
  /src/external/apache2/llvm/dist/llvm/lib/Target/CSKY/AsmParser/
CSKYAsmParser.cpp 90 struct RegOp {
101 RegOp Reg;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64InstructionSelector.cpp 814 MachineOperand &RegOp = I.getOperand(1);
815 RegOp.setReg(SubRegCopy.getReg(0));
941 MachineOperand &RegOp = I.getOperand(1);
942 RegOp.setReg(PromoteReg);
2430 MachineOperand &RegOp = I.getOperand(0);
2431 RegOp.setReg(DefGPRReg);
4887 MachineOperand &RegOp = I.getOperand(1);
4888 RegOp.setReg(Reg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/AsmParser/
LanaiAsmParser.cpp 122 struct RegOp {
139 struct RegOp Reg;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsAsmPrinter.cpp 586 unsigned RegOp = OpNum;
592 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
595 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
598 RegOp = OpNum + 1;
600 if (RegOp >= MI->getNumOperands())
602 const MachineOperand &MO = MI->getOperand(RegOp);
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCMIPeephole.cpp 287 Register RegOp = VisitedPHI->getOperand(PHIOp).getReg();
288 if (!Register::isVirtualRegister(RegOp))
290 MachineInstr *Instr = MRI->getVRegDef(RegOp);
334 Register RegOp = PHI->getOperand(PHIOp).getReg();
335 MachineInstr *PHIInput = MRI->getVRegDef(RegOp);
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/AsmParser/
RISCVAsmParser.cpp 269 struct RegOp {
292 RegOp Reg;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/AsmParser/
SparcAsmParser.cpp 237 struct RegOp {
254 struct RegOp Reg;
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/AsmParser/
X86Operand.h 44 struct RegOp {
74 struct RegOp Reg;
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86MCInstLower.cpp 378 unsigned RegOp = IsStore ? 0 : 5;
381 Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
390 unsigned Reg = Inst.getOperand(RegOp).getReg();
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
GCNHazardRecognizer.cpp 142 const MachineOperand *RegOp = TII->getNamedOperand(RegInstr,
144 return RegOp->getImm() & AMDGPU::Hwreg::ID_MASK_;
SIFoldOperands.cpp 1431 const MachineOperand *RegOp = nullptr;
1437 RegOp = Src1;
1440 RegOp = Src0;
1452 return std::make_pair(RegOp, OMod);
1484 const MachineOperand *RegOp;
1486 std::tie(RegOp, OMod) = isOMod(MI);
1487 if (OMod == SIOutMods::NONE || !RegOp->isReg() ||
1488 RegOp->getSubReg() != AMDGPU::NoSubRegister ||
1489 !MRI->hasOneNonDBGUser(RegOp->getReg()))
1492 MachineInstr *Def = MRI->getVRegDef(RegOp->getReg())
    [all...]
SIInstrInfo.cpp 1098 MachineOperand RegOp = Cond[1];
1099 RegOp.setImplicit(false);
1102 .add(RegOp);
1112 MachineOperand RegOp = Cond[1];
1113 RegOp.setImplicit(false);
1116 .add(RegOp);
2041 MachineOperand &RegOp,
2043 Register Reg = RegOp.getReg();
2044 unsigned SubReg = RegOp.getSubReg();
2045 bool IsKill = RegOp.isKill()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonConstExtenders.cpp 1777 const MachineOperand &RegOp = MI.getOperand(IsAddi ? 1 : 2);
1779 assert(Ex.Rs == RegOp && EV == ImmOp && Ex.Neg != IsAddi &&
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/AsmParser/
SystemZAsmParser.cpp 105 struct RegOp {
135 RegOp Reg;
  /src/external/apache2/llvm/dist/llvm/lib/Target/VE/AsmParser/
VEAsmParser.cpp 172 struct RegOp {
202 struct RegOp Reg;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MachinePipeliner.cpp 395 MachineOperand &RegOp = PI.getOperand(i);
396 if (RegOp.getSubReg() == 0)
406 .addReg(RegOp.getReg(), getRegState(RegOp),
407 RegOp.getSubReg());
409 RegOp.setReg(NewReg);
410 RegOp.setSubReg(0);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/
AArch64AsmParser.cpp 347 struct RegOp {
442 struct RegOp Reg;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/
AMDGPUAsmParser.cpp 183 struct RegOp {
191 RegOp Reg;

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