1 //==-- llvm/CodeGen/GlobalISel/Utils.h ---------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file This file declares the API of helper functions used throughout the 10 /// GlobalISel pipeline. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_CODEGEN_GLOBALISEL_UTILS_H 15 #define LLVM_CODEGEN_GLOBALISEL_UTILS_H 16 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/CodeGen/MachineBasicBlock.h" 19 #include "llvm/CodeGen/Register.h" 20 #include "llvm/Support/Alignment.h" 21 #include "llvm/Support/LowLevelTypeImpl.h" 22 #include <cstdint> 23 24 namespace llvm { 25 26 class AnalysisUsage; 27 class BlockFrequencyInfo; 28 class GISelKnownBits; 29 class MachineFunction; 30 class MachineInstr; 31 class MachineOperand; 32 class MachineOptimizationRemarkEmitter; 33 class MachineOptimizationRemarkMissed; 34 struct MachinePointerInfo; 35 class MachineRegisterInfo; 36 class MCInstrDesc; 37 class ProfileSummaryInfo; 38 class RegisterBankInfo; 39 class TargetInstrInfo; 40 class TargetLowering; 41 class TargetPassConfig; 42 class TargetRegisterInfo; 43 class TargetRegisterClass; 44 class ConstantInt; 45 class ConstantFP; 46 class APFloat; 47 48 // Convenience macros for dealing with vector reduction opcodes. 49 #define GISEL_VECREDUCE_CASES_ALL \ 50 case TargetOpcode::G_VECREDUCE_SEQ_FADD: \ 51 case TargetOpcode::G_VECREDUCE_SEQ_FMUL: \ 52 case TargetOpcode::G_VECREDUCE_FADD: \ 53 case TargetOpcode::G_VECREDUCE_FMUL: \ 54 case TargetOpcode::G_VECREDUCE_FMAX: \ 55 case TargetOpcode::G_VECREDUCE_FMIN: \ 56 case TargetOpcode::G_VECREDUCE_ADD: \ 57 case TargetOpcode::G_VECREDUCE_MUL: \ 58 case TargetOpcode::G_VECREDUCE_AND: \ 59 case TargetOpcode::G_VECREDUCE_OR: \ 60 case TargetOpcode::G_VECREDUCE_XOR: \ 61 case TargetOpcode::G_VECREDUCE_SMAX: \ 62 case TargetOpcode::G_VECREDUCE_SMIN: \ 63 case TargetOpcode::G_VECREDUCE_UMAX: \ 64 case TargetOpcode::G_VECREDUCE_UMIN: 65 66 #define GISEL_VECREDUCE_CASES_NONSEQ \ 67 case TargetOpcode::G_VECREDUCE_FADD: \ 68 case TargetOpcode::G_VECREDUCE_FMUL: \ 69 case TargetOpcode::G_VECREDUCE_FMAX: \ 70 case TargetOpcode::G_VECREDUCE_FMIN: \ 71 case TargetOpcode::G_VECREDUCE_ADD: \ 72 case TargetOpcode::G_VECREDUCE_MUL: \ 73 case TargetOpcode::G_VECREDUCE_AND: \ 74 case TargetOpcode::G_VECREDUCE_OR: \ 75 case TargetOpcode::G_VECREDUCE_XOR: \ 76 case TargetOpcode::G_VECREDUCE_SMAX: \ 77 case TargetOpcode::G_VECREDUCE_SMIN: \ 78 case TargetOpcode::G_VECREDUCE_UMAX: \ 79 case TargetOpcode::G_VECREDUCE_UMIN: 80 81 /// Try to constrain Reg to the specified register class. If this fails, 82 /// create a new virtual register in the correct class. 83 /// 84 /// \return The virtual register constrained to the right register class. 85 Register constrainRegToClass(MachineRegisterInfo &MRI, 86 const TargetInstrInfo &TII, 87 const RegisterBankInfo &RBI, Register Reg, 88 const TargetRegisterClass &RegClass); 89 90 /// Constrain the Register operand OpIdx, so that it is now constrained to the 91 /// TargetRegisterClass passed as an argument (RegClass). 92 /// If this fails, create a new virtual register in the correct class and insert 93 /// a COPY before \p InsertPt if it is a use or after if it is a definition. 94 /// In both cases, the function also updates the register of RegMo. The debug 95 /// location of \p InsertPt is used for the new copy. 96 /// 97 /// \return The virtual register constrained to the right register class. 98 Register constrainOperandRegClass(const MachineFunction &MF, 99 const TargetRegisterInfo &TRI, 100 MachineRegisterInfo &MRI, 101 const TargetInstrInfo &TII, 102 const RegisterBankInfo &RBI, 103 MachineInstr &InsertPt, 104 const TargetRegisterClass &RegClass, 105 MachineOperand &RegMO); 106 107 /// Try to constrain Reg so that it is usable by argument OpIdx of the provided 108 /// MCInstrDesc \p II. If this fails, create a new virtual register in the 109 /// correct class and insert a COPY before \p InsertPt if it is a use or after 110 /// if it is a definition. In both cases, the function also updates the register 111 /// of RegMo. 112 /// This is equivalent to constrainOperandRegClass(..., RegClass, ...) 113 /// with RegClass obtained from the MCInstrDesc. The debug location of \p 114 /// InsertPt is used for the new copy. 115 /// 116 /// \return The virtual register constrained to the right register class. 117 Register constrainOperandRegClass(const MachineFunction &MF, 118 const TargetRegisterInfo &TRI, 119 MachineRegisterInfo &MRI, 120 const TargetInstrInfo &TII, 121 const RegisterBankInfo &RBI, 122 MachineInstr &InsertPt, const MCInstrDesc &II, 123 MachineOperand &RegMO, unsigned OpIdx); 124 125 /// Mutate the newly-selected instruction \p I to constrain its (possibly 126 /// generic) virtual register operands to the instruction's register class. 127 /// This could involve inserting COPYs before (for uses) or after (for defs). 128 /// This requires the number of operands to match the instruction description. 129 /// \returns whether operand regclass constraining succeeded. 130 /// 131 // FIXME: Not all instructions have the same number of operands. We should 132 // probably expose a constrain helper per operand and let the target selector 133 // constrain individual registers, like fast-isel. 134 bool constrainSelectedInstRegOperands(MachineInstr &I, 135 const TargetInstrInfo &TII, 136 const TargetRegisterInfo &TRI, 137 const RegisterBankInfo &RBI); 138 139 /// Check if DstReg can be replaced with SrcReg depending on the register 140 /// constraints. 141 bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI); 142 143 /// Check whether an instruction \p MI is dead: it only defines dead virtual 144 /// registers, and doesn't have other side effects. 145 bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI); 146 147 /// Report an ISel error as a missed optimization remark to the LLVMContext's 148 /// diagnostic stream. Set the FailedISel MachineFunction property. 149 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, 150 MachineOptimizationRemarkEmitter &MORE, 151 MachineOptimizationRemarkMissed &R); 152 153 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, 154 MachineOptimizationRemarkEmitter &MORE, 155 const char *PassName, StringRef Msg, 156 const MachineInstr &MI); 157 158 /// Report an ISel warning as a missed optimization remark to the LLVMContext's 159 /// diagnostic stream. 160 void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC, 161 MachineOptimizationRemarkEmitter &MORE, 162 MachineOptimizationRemarkMissed &R); 163 164 /// If \p VReg is defined by a G_CONSTANT, return the corresponding value. 165 Optional<APInt> getConstantVRegVal(Register VReg, 166 const MachineRegisterInfo &MRI); 167 168 /// If \p VReg is defined by a G_CONSTANT fits in int64_t 169 /// returns it. 170 Optional<int64_t> getConstantVRegSExtVal(Register VReg, 171 const MachineRegisterInfo &MRI); 172 173 /// Simple struct used to hold a constant integer value and a virtual 174 /// register. 175 struct ValueAndVReg { 176 APInt Value; 177 Register VReg; 178 }; 179 /// If \p VReg is defined by a statically evaluable chain of 180 /// instructions rooted on a G_F/CONSTANT (\p LookThroughInstrs == true) 181 /// and that constant fits in int64_t, returns its value as well as the 182 /// virtual register defined by this G_F/CONSTANT. 183 /// When \p LookThroughInstrs == false this function behaves like 184 /// getConstantVRegVal. 185 /// When \p HandleFConstants == false the function bails on G_FCONSTANTs. 186 /// When \p LookThroughAnyExt == true the function treats G_ANYEXT same as 187 /// G_SEXT. 188 Optional<ValueAndVReg> 189 getConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, 190 bool LookThroughInstrs = true, 191 bool HandleFConstants = true, 192 bool LookThroughAnyExt = false); 193 const ConstantInt *getConstantIntVRegVal(Register VReg, 194 const MachineRegisterInfo &MRI); 195 const ConstantFP* getConstantFPVRegVal(Register VReg, 196 const MachineRegisterInfo &MRI); 197 198 /// See if Reg is defined by an single def instruction that is 199 /// Opcode. Also try to do trivial folding if it's a COPY with 200 /// same types. Returns null otherwise. 201 MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg, 202 const MachineRegisterInfo &MRI); 203 204 /// Simple struct used to hold a Register value and the instruction which 205 /// defines it. 206 struct DefinitionAndSourceRegister { 207 MachineInstr *MI; 208 Register Reg; 209 }; 210 211 /// Find the def instruction for \p Reg, and underlying value Register folding 212 /// away any copies. 213 /// 214 /// Also walks through hints such as G_ASSERT_ZEXT. 215 Optional<DefinitionAndSourceRegister> 216 getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI); 217 218 /// Find the def instruction for \p Reg, folding away any trivial copies. May 219 /// return nullptr if \p Reg is not a generic virtual register. 220 /// 221 /// Also walks through hints such as G_ASSERT_ZEXT. 222 MachineInstr *getDefIgnoringCopies(Register Reg, 223 const MachineRegisterInfo &MRI); 224 225 /// Find the source register for \p Reg, folding away any trivial copies. It 226 /// will be an output register of the instruction that getDefIgnoringCopies 227 /// returns. May return an invalid register if \p Reg is not a generic virtual 228 /// register. 229 /// 230 /// Also walks through hints such as G_ASSERT_ZEXT. 231 Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI); 232 233 /// Returns an APFloat from Val converted to the appropriate size. 234 APFloat getAPFloatFromSize(double Val, unsigned Size); 235 236 /// Modify analysis usage so it preserves passes required for the SelectionDAG 237 /// fallback. 238 void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU); 239 240 Optional<APInt> ConstantFoldBinOp(unsigned Opcode, const Register Op1, 241 const Register Op2, 242 const MachineRegisterInfo &MRI); 243 Optional<APFloat> ConstantFoldFPBinOp(unsigned Opcode, const Register Op1, 244 const Register Op2, 245 const MachineRegisterInfo &MRI); 246 247 Optional<APInt> ConstantFoldExtOp(unsigned Opcode, const Register Op1, 248 uint64_t Imm, const MachineRegisterInfo &MRI); 249 250 /// Test if the given value is known to have exactly one bit set. This differs 251 /// from computeKnownBits in that it doesn't necessarily determine which bit is 252 /// set. 253 bool isKnownToBeAPowerOfTwo(Register Val, const MachineRegisterInfo &MRI, 254 GISelKnownBits *KnownBits = nullptr); 255 256 /// Returns true if \p Val can be assumed to never be a NaN. If \p SNaN is true, 257 /// this returns if \p Val can be assumed to never be a signaling NaN. 258 bool isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI, 259 bool SNaN = false); 260 261 /// Returns true if \p Val can be assumed to never be a signaling NaN. 262 inline bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI) { 263 return isKnownNeverNaN(Val, MRI, true); 264 } 265 266 Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO); 267 268 /// Return a virtual register corresponding to the incoming argument register \p 269 /// PhysReg. This register is expected to have class \p RC, and optional type \p 270 /// RegTy. This assumes all references to the register will use the same type. 271 /// 272 /// If there is an existing live-in argument register, it will be returned. 273 /// This will also ensure there is a valid copy 274 Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII, 275 MCRegister PhysReg, 276 const TargetRegisterClass &RC, 277 LLT RegTy = LLT()); 278 279 /// Return the least common multiple type of \p OrigTy and \p TargetTy, by changing the 280 /// number of vector elements or scalar bitwidth. The intent is a 281 /// G_MERGE_VALUES, G_BUILD_VECTOR, or G_CONCAT_VECTORS can be constructed from 282 /// \p OrigTy elements, and unmerged into \p TargetTy 283 LLVM_READNONE 284 LLT getLCMType(LLT OrigTy, LLT TargetTy); 285 286 /// Return a type where the total size is the greatest common divisor of \p 287 /// OrigTy and \p TargetTy. This will try to either change the number of vector 288 /// elements, or bitwidth of scalars. The intent is the result type can be used 289 /// as the result of a G_UNMERGE_VALUES from \p OrigTy, and then some 290 /// combination of G_MERGE_VALUES, G_BUILD_VECTOR and G_CONCAT_VECTORS (possibly 291 /// with intermediate casts) can re-form \p TargetTy. 292 /// 293 /// If these are vectors with different element types, this will try to produce 294 /// a vector with a compatible total size, but the element type of \p OrigTy. If 295 /// this can't be satisfied, this will produce a scalar smaller than the 296 /// original vector elements. 297 /// 298 /// In the worst case, this returns LLT::scalar(1) 299 LLVM_READNONE 300 LLT getGCDType(LLT OrigTy, LLT TargetTy); 301 302 /// Represents a value which can be a Register or a constant. 303 /// 304 /// This is useful in situations where an instruction may have an interesting 305 /// register operand or interesting constant operand. For a concrete example, 306 /// \see getVectorSplat. 307 class RegOrConstant { 308 int64_t Cst; 309 Register Reg; 310 bool IsReg; 311 312 public: 313 explicit RegOrConstant(Register Reg) : Reg(Reg), IsReg(true) {} 314 explicit RegOrConstant(int64_t Cst) : Cst(Cst), IsReg(false) {} 315 bool isReg() const { return IsReg; } 316 bool isCst() const { return !IsReg; } 317 Register getReg() const { 318 assert(isReg() && "Expected a register!"); 319 return Reg; 320 } 321 int64_t getCst() const { 322 assert(isCst() && "Expected a constant!"); 323 return Cst; 324 } 325 }; 326 327 /// \returns The splat index of a G_SHUFFLE_VECTOR \p MI when \p MI is a splat. 328 /// If \p MI is not a splat, returns None. 329 Optional<int> getSplatIndex(MachineInstr &MI); 330 331 /// Returns a scalar constant of a G_BUILD_VECTOR splat if it exists. 332 Optional<int64_t> getBuildVectorConstantSplat(const MachineInstr &MI, 333 const MachineRegisterInfo &MRI); 334 335 /// Return true if the specified instruction is a G_BUILD_VECTOR or 336 /// G_BUILD_VECTOR_TRUNC where all of the elements are 0 or undef. 337 bool isBuildVectorAllZeros(const MachineInstr &MI, 338 const MachineRegisterInfo &MRI); 339 340 /// Return true if the specified instruction is a G_BUILD_VECTOR or 341 /// G_BUILD_VECTOR_TRUNC where all of the elements are ~0 or undef. 342 bool isBuildVectorAllOnes(const MachineInstr &MI, 343 const MachineRegisterInfo &MRI); 344 345 /// \returns a value when \p MI is a vector splat. The splat can be either a 346 /// Register or a constant. 347 /// 348 /// Examples: 349 /// 350 /// \code 351 /// %reg = COPY $physreg 352 /// %reg_splat = G_BUILD_VECTOR %reg, %reg, ..., %reg 353 /// \endcode 354 /// 355 /// If called on the G_BUILD_VECTOR above, this will return a RegOrConstant 356 /// containing %reg. 357 /// 358 /// \code 359 /// %cst = G_CONSTANT iN 4 360 /// %constant_splat = G_BUILD_VECTOR %cst, %cst, ..., %cst 361 /// \endcode 362 /// 363 /// In the above case, this will return a RegOrConstant containing 4. 364 Optional<RegOrConstant> getVectorSplat(const MachineInstr &MI, 365 const MachineRegisterInfo &MRI); 366 367 /// Attempt to match a unary predicate against a scalar/splat constant or every 368 /// element of a constant G_BUILD_VECTOR. If \p ConstVal is null, the source 369 /// value was undef. 370 bool matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg, 371 std::function<bool(const Constant *ConstVal)> Match, 372 bool AllowUndefs = false); 373 374 /// Returns true if given the TargetLowering's boolean contents information, 375 /// the value \p Val contains a true value. 376 bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector, 377 bool IsFP); 378 379 /// Returns an integer representing true, as defined by the 380 /// TargetBooleanContents. 381 int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP); 382 383 /// Returns true if the given block should be optimized for size. 384 bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, 385 BlockFrequencyInfo *BFI); 386 387 /// \returns the intrinsic ID for a G_INTRINSIC or G_INTRINSIC_W_SIDE_EFFECTS 388 /// instruction \p MI. 389 unsigned getIntrinsicID(const MachineInstr &MI); 390 391 } // End namespace llvm. 392 #endif 393
Indexes created Mon Jun 08 00:24:58 UTC 2026