HomeSort by: relevance | last modified time | path
    Searched defs:RegTy (Results 1 - 9 of 9) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
RegBankSelect.cpp 174 LLT RegTy = MRI->getType(MO.getReg());
177 if (RegTy.isVector()) {
178 if (ValMapping.NumBreakDowns == RegTy.getNumElements())
183 RegTy.getSizeInBits()) &&
184 (ValMapping.BreakDown[0].Length % RegTy.getScalarSizeInBits() ==
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MachineRegisterInfo.cpp 95 const LLT RegTy = getType(Reg);
97 if (RegTy.isValid() && ConstrainingRegTy.isValid() &&
98 RegTy != ConstrainingRegTy)
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsRegisterBankInfo.cpp 453 LLT RegTy = MRI.getType(Op.getReg());
455 if (RegTy.isScalar() &&
456 (RegTy.getSizeInBits() != 32 && RegTy.getSizeInBits() != 64))
459 if (RegTy.isVector() && RegTy.getSizeInBits() != 128)
MipsISelLowering.cpp 4352 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8);
4353 const TargetRegisterClass *RC = getRegClassFor(RegTy);
4361 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
4381 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
4393 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
4420 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
4432 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
4436 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
4471 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
4472 const TargetRegisterClass *RC = getRegClassFor(RegTy);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64CallLowering.cpp 307 const LLT RegTy = MRI.getType(ValVReg);
309 if (RegTy.getSizeInBits() < LocVT.getSizeInBits())
310 ValVReg = MIRBuilder.buildTrunc(RegTy, ValVReg).getReg(0);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUCallLowering.cpp 130 const LLT RegTy = MRI.getType(ValVReg);
131 MemSize = std::min(static_cast<uint64_t>(RegTy.getSizeInBytes()), MemSize);
240 const LLT RegTy = MRI.getType(ValVReg);
241 MemSize = std::min(MemSize, (uint64_t)RegTy.getSizeInBytes());
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstructionSelector.cpp 1487 const LLT RegTy = MRI.getType(DstReg);
1488 assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) &&
1562 auto OpEntryIt = llvm::find_if(OpTable, [RegTy](const DivRemEntry &El) {
1563 return El.SizeInBits == RegTy.getSizeInBits();
1589 const TargetRegisterClass *RegRC = getRegClass(RegTy, *RegRB);
1615 if (RegTy.getSizeInBits() == 16) {
1619 } else if (RegTy.getSizeInBits() == 32) {
1623 } else if (RegTy.getSizeInBits() == 64) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/AsmParser/
HexagonAsmParser.cpp 206 struct RegTy {
220 struct RegTy Reg;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelDAGToDAG.cpp 3058 MVT RegTy = MemTy == MVT::i64 ? MVT::i64 : MVT::i32;
3063 CurDAG->getVTList(RegTy, MVT::i32, MVT::Other), Ops);

Completed in 37 milliseconds