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    Searched defs:RegUnit (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
RegisterPressure.h 40 Register RegUnit; ///< Virtual register or register unit.
43 RegisterMaskPair(Register RegUnit, LaneBitmask LaneMask)
44 : RegUnit(RegUnit), LaneMask(LaneMask) {}
160 void addPressureChange(Register RegUnit, bool IsDec,
306 unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit);
319 unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit);
551 void increaseRegPressure(Register RegUnit, LaneBitmask PreviousMask,
553 void decreaseRegPressure(Register RegUnit, LaneBitmask PreviousMask,
564 LaneBitmask getLastUsedLanes(Register RegUnit, SlotIndex Pos) const
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MachineTraceMetrics.h 72 // Associate each regunit with an instruction operand. Depending on the
74 // regunit, or the highest operand to read the regunit.
76 unsigned RegUnit;
81 unsigned getSparseSetIndex() const { return RegUnit; }
83 LiveRegUnit(unsigned RU) : RegUnit(RU) {}
139 /// A virtual register or regunit required by a basic block or its trace
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
RegisterPressure.cpp 100 dbgs() << printVRegOrUnit(P.RegUnit, TRI);
108 dbgs() << printVRegOrUnit(P.RegUnit, TRI);
155 void RegPressureTracker::increaseRegPressure(Register RegUnit,
161 PSetIterator PSetI = MRI->getPressureSets(RegUnit);
170 void RegPressureTracker::decreaseRegPressure(Register RegUnit,
173 decreaseSetPressure(CurrSetPressure, *MRI, RegUnit, PreviousMask, NewMask);
363 Register RegUnit = Pair.RegUnit;
364 if (Register::isVirtualRegister(RegUnit)
365 && !RPTracker.hasUntiedDef(RegUnit))
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  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIOptimizeExecMaskingPreRA.cpp 285 LiveRange &RegUnit = LIS->getRegUnit(*UI);
286 if (RegUnit.find(StartIdx) != std::prev(RegUnit.find(EndIdx)))
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenRegisters.h 484 struct RegUnit {
485 // Weight assigned to this RegUnit for estimating register pressure.
490 // Each native RegUnit corresponds to one or two root registers. The full
502 RegUnit() : Weight(0), RegClassUnitSetsIdx(0), Artificial(false) {
553 SmallVector<RegUnit, 8> RegUnits;
567 // class's units and any inferred RegUnit supersets.
684 RegUnit &RU = RegUnits.back();
712 RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; }
713 const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; }

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