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      1 //===- RegisterClassInfo.h - Dynamic Register Class Info --------*- C++ -*-===//
      2 //
      3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
      4 // See https://llvm.org/LICENSE.txt for license information.
      5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
      6 //
      7 //===----------------------------------------------------------------------===//
      8 //
      9 // This file implements the RegisterClassInfo class which provides dynamic
     10 // information about target register classes. Callee saved and reserved
     11 // registers depends on calling conventions and other dynamic information, so
     12 // some things cannot be determined statically.
     13 //
     14 //===----------------------------------------------------------------------===//
     15 
     16 #ifndef LLVM_CODEGEN_REGISTERCLASSINFO_H
     17 #define LLVM_CODEGEN_REGISTERCLASSINFO_H
     18 
     19 #include "llvm/ADT/ArrayRef.h"
     20 #include "llvm/ADT/BitVector.h"
     21 #include "llvm/ADT/SmallVector.h"
     22 #include "llvm/CodeGen/TargetRegisterInfo.h"
     23 #include "llvm/MC/MCRegisterInfo.h"
     24 #include <cassert>
     25 #include <cstdint>
     26 #include <memory>
     27 
     28 namespace llvm {
     29 
     30 class RegisterClassInfo {
     31   struct RCInfo {
     32     unsigned Tag = 0;
     33     unsigned NumRegs = 0;
     34     bool ProperSubClass = false;
     35     uint8_t MinCost = 0;
     36     uint16_t LastCostChange = 0;
     37     std::unique_ptr<MCPhysReg[]> Order;
     38 
     39     RCInfo() = default;
     40 
     41     operator ArrayRef<MCPhysReg>() const {
     42       return makeArrayRef(Order.get(), NumRegs);
     43     }
     44   };
     45 
     46   // Brief cached information for each register class.
     47   std::unique_ptr<RCInfo[]> RegClass;
     48 
     49   // Tag changes whenever cached information needs to be recomputed. An RCInfo
     50   // entry is valid when its tag matches.
     51   unsigned Tag = 0;
     52 
     53   const MachineFunction *MF = nullptr;
     54   const TargetRegisterInfo *TRI = nullptr;
     55 
     56   // Callee saved registers of last MF. Assumed to be valid until the next
     57   // runOnFunction() call.
     58   // Used only to determine if an update was made to CalleeSavedAliases.
     59   const MCPhysReg *CalleeSavedRegs = nullptr;
     60 
     61   // Map register alias to the callee saved Register.
     62   SmallVector<MCPhysReg, 4> CalleeSavedAliases;
     63 
     64   // Reserved registers in the current MF.
     65   BitVector Reserved;
     66 
     67   std::unique_ptr<unsigned[]> PSetLimits;
     68 
     69   // The register cost values.
     70   ArrayRef<uint8_t> RegCosts;
     71 
     72   // Compute all information about RC.
     73   void compute(const TargetRegisterClass *RC) const;
     74 
     75   // Return an up-to-date RCInfo for RC.
     76   const RCInfo &get(const TargetRegisterClass *RC) const {
     77     const RCInfo &RCI = RegClass[RC->getID()];
     78     if (Tag != RCI.Tag)
     79       compute(RC);
     80     return RCI;
     81   }
     82 
     83 public:
     84   RegisterClassInfo();
     85 
     86   /// runOnFunction - Prepare to answer questions about MF. This must be called
     87   /// before any other methods are used.
     88   void runOnMachineFunction(const MachineFunction &MF);
     89 
     90   /// getNumAllocatableRegs - Returns the number of actually allocatable
     91   /// registers in RC in the current function.
     92   unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const {
     93     return get(RC).NumRegs;
     94   }
     95 
     96   /// getOrder - Returns the preferred allocation order for RC. The order
     97   /// contains no reserved registers, and registers that alias callee saved
     98   /// registers come last.
     99   ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const {
    100     return get(RC);
    101   }
    102 
    103   /// isProperSubClass - Returns true if RC has a legal super-class with more
    104   /// allocatable registers.
    105   ///
    106   /// Register classes like GR32_NOSP are not proper sub-classes because %esp
    107   /// is not allocatable.  Similarly, tGPR is not a proper sub-class in Thumb
    108   /// mode because the GPR super-class is not legal.
    109   bool isProperSubClass(const TargetRegisterClass *RC) const {
    110     return get(RC).ProperSubClass;
    111   }
    112 
    113   /// getLastCalleeSavedAlias - Returns the last callee saved register that
    114   /// overlaps PhysReg, or NoRegister if Reg doesn't overlap a
    115   /// CalleeSavedAliases.
    116   MCRegister getLastCalleeSavedAlias(MCRegister PhysReg) const {
    117     if (PhysReg.id() < CalleeSavedAliases.size())
    118       return CalleeSavedAliases[PhysReg];
    119     return MCRegister::NoRegister;
    120   }
    121 
    122   /// Get the minimum register cost in RC's allocation order.
    123   /// This is the smallest value in RegCosts[Reg] for all
    124   /// the registers in getOrder(RC).
    125   uint8_t getMinCost(const TargetRegisterClass *RC) const {
    126     return get(RC).MinCost;
    127   }
    128 
    129   /// Get the position of the last cost change in getOrder(RC).
    130   ///
    131   /// All registers in getOrder(RC).slice(getLastCostChange(RC)) will have the
    132   /// same cost according to RegCosts[Reg].
    133   unsigned getLastCostChange(const TargetRegisterClass *RC) const {
    134     return get(RC).LastCostChange;
    135   }
    136 
    137   /// Get the register unit limit for the given pressure set index.
    138   ///
    139   /// RegisterClassInfo adjusts this limit for reserved registers.
    140   unsigned getRegPressureSetLimit(unsigned Idx) const {
    141     if (!PSetLimits[Idx])
    142       PSetLimits[Idx] = computePSetLimit(Idx);
    143     return PSetLimits[Idx];
    144   }
    145 
    146 protected:
    147   unsigned computePSetLimit(unsigned Idx) const;
    148 };
    149 
    150 } // end namespace llvm
    151 
    152 #endif // LLVM_CODEGEN_REGISTERCLASSINFO_H
    153