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    Searched defs:RegisterVT (Results 1 - 9 of 9) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyMachineFunctionInfo.cpp 43 MVT RegisterVT = TLI.getRegisterType(F.getContext(), VT);
45 ValueVTs.push_back(RegisterVT);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
FunctionLoweringInfo.cpp 395 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
399 Register R = CreateReg(RegisterVT, isDivergent);
FastISel.cpp 1014 MVT RegisterVT = TLI.getRegisterType(CLI.RetTy->getContext(), VT);
1018 MyFlags.VT = RegisterVT;
SelectionDAGBuilder.cpp 340 MVT RegisterVT;
347 NumIntermediates, RegisterVT);
351 NumIntermediates, RegisterVT);
356 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
357 assert(RegisterVT.getSizeInBits() ==
694 MVT RegisterVT;
700 NumIntermediates, RegisterVT);
704 NumIntermediates, RegisterVT);
709 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
794 MVT RegisterVT
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsCallLowering.cpp 73 MVT RegisterVT = TLI.getRegisterTypeForCallingConv(
76 VRegs.push_back(MRI.createGenericVirtualRegister(LLT{RegisterVT}));
347 static CCValAssign::LocInfo determineLocInfo(const MVT RegisterVT, const EVT VT,
349 // > does not mean loss of information as type RegisterVT can't hold type VT,
350 // it means that type VT is split into multiple registers of type RegisterVT
351 if (VT.getFixedSizeInBits() >= RegisterVT.getFixedSizeInBits())
648 MVT RegisterVT = TLI.getRegisterTypeForCallingConv(F.getContext(),
661 ISDArgs.emplace_back(Flags, RegisterVT, VT, true, OrigArgIndices[ArgNo],
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetLoweringBase.cpp 1071 MVT &RegisterVT,
1116 RegisterVT = DestVT;
1437 MVT RegisterVT;
1440 NumIntermediates, RegisterVT, this);
1444 RegisterTypeForVT[i] = RegisterVT;
1506 MVT &RegisterVT) const {
1520 RegisterVT = RegisterEVT.getSimpleVT();
1553 RegisterVT = getRegisterType(Context, IntermediateVT);
1580 RegisterVT = DestVT;
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp 2157 MVT RegisterVT;
2159 std::tie(RegisterVT, NumRegisters) =
2161 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
2162 return RegisterVT;
2175 MVT RegisterVT;
2177 std::tie(RegisterVT, NumRegisters) =
2179 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
2188 unsigned &NumIntermediates, MVT &RegisterVT) const {
2195 RegisterVT = MVT::i8;
2204 RegisterVT = MVT::v32i8
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
TargetLowering.h 970 MVT &RegisterVT) const;
977 unsigned &NumIntermediates, MVT &RegisterVT) const {
979 RegisterVT);
1455 MVT RegisterVT;
1458 NumIntermediates, RegisterVT);
1459 return RegisterVT;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUISelLowering.cpp 1054 MVT RegisterVT = getRegisterTypeForCallingConv(Ctx, CC, ArgVT);
1062 MemVT = RegisterVT;
1066 } else if (ArgVT.isVector() && RegisterVT.isVector() &&
1067 ArgVT.getScalarType() == RegisterVT.getScalarType()) {
1068 assert(ArgVT.getVectorNumElements() > RegisterVT.getVectorNumElements());
1072 MemVT = RegisterVT;
1080 MemVT = RegisterVT;
1084 if (RegisterVT.isInteger()) {
1086 } else if (RegisterVT.isVector()) {
1087 assert(!RegisterVT.getScalarType().isFloatingPoint())
    [all...]

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