1 /* $NetBSD: s3c2800reg.h,v 1.8 2022/05/23 21:46:11 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Fujitsu Component Limited 5 * Copyright (c) 2002, 2003, 2005 Genetec Corporation 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of The Fujitsu Component Limited nor the name of 17 * Genetec corporation may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC 21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC 25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 /* 36 * Samsung S3C2800 processor is ARM920T based integrated CPU 37 * 38 * Reference: 39 * S3C2800 User's Manual 40 */ 41 #ifndef _ARM_S3C2XX0_S3C2800REG_H_ 42 #define _ARM_S3C2XX0_S3C2800REG_H_ 43 44 /* common definitions for S3C2800, S3C2400 and S3C2410 */ 45 #include <arm/s3c2xx0/s3c2xx0reg.h> 46 47 /* 48 * Memory Map 49 */ 50 51 /* ROM/SRAM/FLASH */ 52 #define S3C2800_SBANK0_START 0x00000000 53 #define S3C2800_SBANK1_START 0x02000000 54 #define S3C2800_SBANK2_START 0x04000000 55 #define S3C2800_SBANK3_START 0x06000000 56 #define S3C2800_SBANK4_START 0x08000000 57 58 /* DRAM */ 59 #define S3C2800_DBANK0_START 0x08000000 60 #define S3C2800_DBANK1_START 0x0a000000 61 #define S3C2800_DBANK2_START 0x0c000000 62 #define S3C2800_DBANK3_START 0x0e000000 63 #define S3C2800_DBANK_SIZE 0x02000000 /* 32MB */ 64 65 /* 66 * Physical address of integrated peripherals 67 */ 68 #define S3C2800_PERIPHERALS 0x10000000 69 #define S3C2800_PERIPHERALS_SIZE 0x200000 /* 2MBytes */ 70 #define S3C2800_CLKMAN_BASE 0x10000000 /* clock & power management */ 71 #define S3C2800_CLKMAN_SIZE 0x18 72 #define S3C2800_MEMCTL_BASE 0x10010000 /* memory controller */ 73 #define S3C2800_MEMCTL_SIZE 0x20 74 #define S3C2800_DMA0_BASE 0x10030000 75 #define S3C2800_DMA1_BASE 0x10040000 76 #define S3C2800_DMA2_BASE 0x10050000 77 #define S3C2800_DMA3_BASE 0x10060000 78 #define S3C2800_PCICTL_BASE 0x10080000 79 #define S3C2800_PCICTL_SIZE 0x58 80 #define S3C2800_GPIO_BASE 0x10100000 81 #define S3C2800_GPIO_SIZE 0x50 82 #define S3C2800_TIMER0_BASE 0x10130000 83 #define S3C2800_TIMER1_BASE 0x10140000 84 #define S3C2800_TIMER2_BASE 0x10150000 85 #define S3C2800_TIMER_SIZE 0x10 86 #define S3C2800_UART0_BASE 0x10170000 87 #define S3C2800_UART1_BASE 0x10180000 88 #define S3C2800_UART_SIZE 0x2c 89 #define S3C2800_IIC0_BASE 0x10190000 90 #define S3C2800_IIC1_BASE 0x101a0000 91 #define S3C2800_IIC_SIZE 0x10 92 #define S3C2800_INTCTL_BASE 0x10020000 93 #define S3C2800_INTCTL_SIZE 0x14 94 #define S3C2800_WDT_BASE 0x10120000 95 #define S3C2800_WDT_SIZE 0x0c 96 97 98 /* width of interrupt controller */ 99 #define ICU_LEN 29 100 #define ICU_INT_HWMASK 0x1fffffff 101 102 /* Clock & power manager */ 103 #define CLKMAN_PLLCON 0x00 104 105 /* MDIV, PDIV, SDIV */ 106 #define PLLCON_MDIV_SHIFT 12 107 #define PLLCON_MDIV_MASK (0xff<<PLLCON_MDIV_SHIFT) 108 #define PLLCON_PDIV_SHIFT 4 109 #define PLLCON_PDIV_MASK (0x3f<<PLLCON_PDIV_SHIFT) 110 #define PLLCON_SDIV_SHIFT 0 111 #define PLLCON_SDIV_MASK (0x03<<PLLCON_SDIV_SHIFT) 112 113 #define CLKMAN_CLKCON 0x04 114 #define CLKCON_PCLK (1<<12) /* APB clock division ratio */ 115 #define CLKCON_HCLK (1<<11) /* AHB clock division ratio */ 116 #define CLKCON_PCI (1<<10) /* FCLK into PCI */ 117 #define CLKCON_IIC1 (1<<9) /* PCLK to I2C1 */ 118 #define CLKCON_IIC0 (1<<8) /* PCLK to I2C0 */ 119 #define CLKCON_RTC (1<<7) /* PCLK to RTC */ 120 #define CLKCON_UART1 (1<<6) /* PCLK to UART1 */ 121 #define CLKCON_UART0 (1<<5) /* PCLK to UART0 */ 122 #define CLKCON_DMA23 (1<<4) /* PCLK to DMA2,3 */ 123 #define CLKCON_DMA01 (1<<3) /* PCLK to DMA0,1 */ 124 #define CLKCON_TIMER (1<<2) /* PCLK to TIMER */ 125 #define CLKCON_IDLE (1<<1) /* Enter IDLE Mode */ 126 127 #define CLKMAN_CLKSLOW 0x08 /* slow clock control */ 128 #define CLKSLOW_SLOW (1<<4) /* 1: Enable SLOW mode */ 129 #define CLKSLOW_VAL_MASK 0x0f /* divider value for slow clock */ 130 131 #define CLKMAN_LOCKTIME 0x0c /* PLL lock time */ 132 133 #define CLKMAN_SWRCON 0x10 /* Software reset control */ 134 #define SWRCON_SWR (1<<0) /* 1: Invoke software reset */ 135 136 #define CLKMAN_RSTSR 0x14 /* Reset status register */ 137 #define RSTSR_WDR (1<<2) /* watchdog reset */ 138 #define RSTSR_SWR (1<<1) /* Software reset */ 139 #define RSTSR_HWR (1<<0) /* Hardware reset */ 140 141 /* memory controller */ 142 #define MEMCTL_ENDIAN 0x00 /* Endian control (read-only) */ 143 #define MEMCTL_SMBCON0 0x04 /* SBank0 control register for static */ 144 #define MEMCTL_SMBCON1 0x08 /* SBank0 control register for static */ 145 #define MEMCTL_SMBCON2 0x0c /* SBank0 control register for static */ 146 #define MEMCTL_SMBCON3 0x10 /* SBank0 control register for static */ 147 #define SMBCON_WS (1<<20) /* Wait status */ 148 #define SMBCON_ST (1<<19) /* use UB/LB */ 149 #define SMBCON_TACS_SHIFT 12 /* address setup time before nSCSn */ 150 #define SMBCON_TACS (3<<SMBCON_TACS_SHIFT) 151 #define SMBCON_TCOS_SHIFT 10 /* CS setup time before nOE */ 152 #define SMBCON_TCOS (3<<SMBCON_TCOS_SHIFT) 153 #define SMBCON_TOCH_SHIFT 8 /* CS hold time after nOE */ 154 #define SMBCON_TOCH (3<<SMBCON_TOCH_SHIFT) 155 #define SMBCON_TACC_SHIFT 4 /* Access cycle */ 156 #define SMBCON_TACC (0x0f<<SMBCON_TOCH_SHIFT) 157 #define SMBCON_TACC_1CLK (0x00<<SMBCON_TOCH_SHIFT) 158 #define SMBCON_TACC_2CLK (0x01<<SMBCON_TOCH_SHIFT) 159 #define SMBCON_TACC_3CLK (0x02<<SMBCON_TOCH_SHIFT) 160 #define SMBCON_TACC_4CLK (0x03<<SMBCON_TOCH_SHIFT) 161 #define SMBCON_TACC_6CLK (0x04<<SMBCON_TOCH_SHIFT) 162 #define SMBCON_TACC_7CLK (0x05<<SMBCON_TOCH_SHIFT) 163 #define SMBCON_TACC_8CLK (0x06<<SMBCON_TOCH_SHIFT) 164 #define SMBCON_TACC_9CLK (0x07<<SMBCON_TOCH_SHIFT) 165 #define SMBCON_TACC_10CLK (0x08<<SMBCON_TOCH_SHIFT) 166 #define SMBCON_TACC_12CLK (0x09<<SMBCON_TOCH_SHIFT) 167 #define SMBCON_TACC_14CLK (0x0a<<SMBCON_TOCH_SHIFT) 168 #define SMBCON_TCAH_SHIFT 2 /* Address hold time after nSCSn */ 169 #define SMBCON_SDW 0x03 170 #define SMBCON_SDW_8BIT 0 171 #define SMBCON_SDW_16BIT 1 172 #define SMBCON_SDW_32BIT 2 173 #define MEMCTL_REFRESH 0x14 /* DRAM/SDRAM refresh control */ 174 #define REFRESH_REFEN (1<<23) 175 #define REFRESH_REFMD (1<<22) 176 #define REFRESH_TRP (3<<20) 177 #define REFRESH_TRC (3<<16) 178 #define REFRESH_TCHR (3<<12) /* CAS hold time */ 179 #define REFRESH_COUNTER 0x7ff 180 #define MEMCTL_DMTMCON 0x18 /* timing control for dynamic memory */ 181 #define DMTMCON_DW_SHIFT 16 182 #define DMTMCON_DW (3<<DMTMCON_DW_SHIFT) /* bus width */ 183 #define DMTMCON_MT (3<<10) /* dynamic memory type */ 184 #define DMTMCON_TRCD (3<<8) /* DRAM RAS to CAS delay */ 185 #define DMTMCON_TCAS (3<<6) /* CAS pulse width */ 186 #define DMTMCON_TCP (3<<4) /* CAS pre charge */ 187 #define DMTMCON_CAN (3<<2) /* column address number */ 188 #define DMTMCON_STRCD (3<<0) /* SDRAM RAS to CAS delay */ 189 #define MEMCTL_MRSR 0x1c /* SDRAM mode register */ 190 #define MRSR_CL_SHIFT 4 191 #define MRSR_CL (7<<MRSR_CL_SHIFT) /* CAS latency */ 192 193 /* GPIO */ 194 #define GPIO_PCONA 0x00 /* port A configuration */ 195 #define PCON_INPUT 0 /* Input port */ 196 #define PCON_OUTPUT 1 /* Output port */ 197 #define PCON_ALTFUN 2 /* Alternate function */ 198 #define GPIO_PDATA 0x04 /* port A data */ 199 #define GPIO_PUPA 0x08 /* port A pull-up */ 200 #define GPIO_PCONB 0x0c 201 #define GPIO_PDATB 0x10 202 #define GPIO_PCONC 0x18 203 #define GPIO_PDATC 0x1c 204 #define GPIO_PUPC 0x20 205 #define GPIO_PCOND 0x24 206 #define GPIO_PDATD 0x28 207 #define GPIO_PUPD 0x2c 208 #define GPIO_PCONE 0x30 209 #define GPIO_PDATE 0x34 210 #define GPIO_PUPE 0x38 211 #define GPIO_PCONF 0x3c 212 #define GPIO_PDATF 0x40 213 #define GPIO_PUPF 0x44 214 215 #define GPIO_EXTINTR 0x48 /* external interrupt control */ 216 #define EXTINTR_LOW 0x00 217 #define EXTINTR_HIGH 0x01 218 #define EXTINTR_FALLING 0x02 219 #define EXTINTR_RISING 0x04 220 #define EXTINTR_BOTH 0x06 221 222 #define GPIO_SPUCR 0x4c /* special pull-up control */ 223 #define SPUCR1 (1<<1) /* pull-up for data[31:16] */ 224 #define SPUCR0 (1<<0) /* pull-up for data[15:0] */ 225 226 /* Timer */ 227 #define TIMER_TMCON 0x00 /* control register */ 228 #define TMCON_MUX (3<<2) /* MUX input */ 229 #define TMCON_MUX_DIV4 (0<<2) 230 #define TMCON_MUX_DIV8 (1<<2) 231 #define TMCON_MUX_DIV16 (2<<2) 232 #define TMCON_MUX_DIV32 (3<<2) 233 #define TMCON_INTENA (1<<1) /* Interrupt/DMA enable */ 234 #define TMCON_ENABLE (1<<0) /* Count enable */ 235 #define TIMER_TMDAT 0x04 /* data register */ 236 #define TMDAT_PRESCALER (0xff<<16) 237 #define TMDAT_DATA 0xffff 238 #define TIMER_TMCNT 0x08 /* down counter */ 239 240 /* UART (Small diffs to S3C2400's UART) */ 241 #define UMCON_AFC (1<<1) /* auto flow control */ 242 #define UMSTAT_DCTS (1<<1) /* CTS change */ 243 244 /* Interrupt controller */ 245 #define INTCTL_IRQPND 0x0c /* IRQ pending */ 246 #define INTCTL_FIQPND 0x10 /* FIQ pending */ 247 248 /* Interrupt source */ 249 #define S3C2800_INT_RTC 28 /* RTC alarm */ 250 #define S3C2800_INT_TICK 27 /* RTC tick */ 251 #define S3C2800_INT_FULL 26 /* Remocon data FIFO full */ 252 #define S3C2800_INT_RMT 25 /* Remocon data input */ 253 #define S3C2800_INT_UERR1 24 /* UART1 error */ 254 #define S3C2800_INT_UERR0 23 /* UART0 error */ 255 #define S3C2800_INT_TXD1 22 /* UART1 Tx */ 256 #define S3C2800_INT_TXD0 21 /* UART0 Tx */ 257 #define S3C2800_INT_RXD1 20 /* UART1 Rx */ 258 #define S3C2800_INT_RXD0 19 /* UART0 Rx*/ 259 #define S3C2800_INT_IIC1 18 260 #define S3C2800_INT_IIC0 17 261 #define S3C2800_INT_TIMER2 16 262 #define S3C2800_INT_TIMER1 15 263 #define S3C2800_INT_TIMER0 14 264 #define S3C2800_INT_DMA3 13 265 #define S3C2800_INT_DMA2 12 266 #define S3C2800_INT_DMA1 11 267 #define S3C2800_INT_DMA0 10 268 #define S3C2800_INT_PCI 8 /* PCI interrupt */ 269 #define S3C2800_INT_EXT(n) (n) /* External interrupt [7:0] */ 270 271 272 /* PCI space */ 273 #define S3C2800_PCI_BASE 0x20000000 274 #define S3C2800_PCI_MEMSPACE_BASE 0x20000000 /* Memory space */ 275 #define S3C2800_PCI_MEMSPACE_SIZE 0x08000000 276 #define S3C2800_PCI_CONF0_BASE 0x28000000 /* Config type 0 space */ 277 #define S3C2800_PCI_CONF0_SIZE 0x0000b000 278 #define S3C2800_PCI_CONF1_BASE 0x2a000000 /* Config type 1 space */ 279 #define S3C2800_PCI_CONF1_SIZE 0x02000000 280 #define S3C2800_PCI_IOSPACE_BASE 0x2e000000 281 #define S3C2800_PCI_IOSPACE_SIZE 0x00100000 282 283 #define PCICTL_PCICON 0x0100 /* control and status */ 284 #define PCICON_INT (1<<31) /* internal interrupt status */ 285 #define PCICON_MBS (1<<29) /* PCI master interface busy */ 286 #define PCICON_TBS (1<<28) /* PCI target interface busy */ 287 #define PCICON_CRS (1<<27) /* ARM CPU reset status */ 288 #define PCICON_RDY (1<<9) /* Enable PCI target read */ 289 #define PCICON_CFD (1<<8) /* Configuration done */ 290 #define PCICON_ATS (1<<4) /* Enable address translation */ 291 #define PCICON_ARB (1<<1) /* Enable internal arbiter */ 292 #define PCICON_HST (1<<0) /* bridge/adaptor */ 293 294 #define PCICTL_PCISET 0x104 /* PCI command, read count, DAC */ 295 #define PCISET_CMD_SHIFT 17 296 #define PCISET_DAC_MASK 0xff 297 298 #define PCICTL_PCIINTEN 0x108 /* interrupt enable */ 299 #define PCICTL_PCIINTST 0x10c /* interrupt status */ 300 301 #define PCIINTEN_BAP (1<<31) /* INTA# in adapter mode */ 302 #define PCIINTST_WDE (1<<31) /* master fatal error in read */ 303 #define PCIINTST_RDE (1<<30) /* master fatal error in write */ 304 #define PCIINT_INA (1<<10) /* INTA# enable */ 305 #define PCIINT_SER (1<<9) /* SERR# interrupt enable */ 306 #define PCIINT_TPE (1<<4) /* target parity error */ 307 #define PCIINT_MPE (1<<3) /* master parity error */ 308 #define PCIINT_MFE (1<<2) /* master fatal error */ 309 #define PCIINT_PRA (1<<1) /* reset assert interrupt */ 310 #define PCIINT_PRD (1<<0) /* reset de-assert interrupt */ 311 312 #define PCICTL_PCIBATPA0 0x140 /* address translation PCI to AHB BAR0 */ 313 #define PCICTL_PCIBAM0 0x144 /* BAR0 mask */ 314 #define PCICTL_PCIBATPA1 0x148 /* address translation PCI to AHB BAR1 */ 315 #define PCICTL_PCIBAM1 0x14c /* BAR0 mask */ 316 #define PCICTL_PCIBATPA2 0x150 /* address translation PCI to AHB BAR2 */ 317 #define PCICTL_PCIBAM2 0x154 /* BAR0 mask */ 318 319 /* Watch dog timer */ 320 #define WDT_WTPSCLR 0x00 321 #define WDT_WTCON 0x04 322 #define WTCON_WDTSTOP 0xa5 323 #define WDT_WTCNT 0x08 324 325 #endif /* _ARM_S3C2XX0_S3C2800REG_H_ */ 326
Indexes created Sat Sep 20 22:09:52 GMT 2025