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      1 /*	$NetBSD: sa11x0_reg.h,v 1.7 2008/04/28 20:23:14 martin Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2001 The NetBSD Foundation, Inc.  All rights reserved.
      5  *
      6  * This code is derived from software contributed to The NetBSD Foundation
      7  * by IWAMOTO Toshihiro.
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  * 1. Redistributions of source code must retain the above copyright
     13  *    notice, this list of conditions and the following disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  *
     18  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     19  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     20  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     21  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     28  * POSSIBILITY OF SUCH DAMAGE.
     29  */
     30 
     31 #ifndef _ARM_SA11X0_REG_H_
     32 #define _ARM_SA11X0_REG_H_
     33 
     34 /* Physical register base addresses */
     35 #define SAOST_BASE		0x90000000	/* OS Timer */
     36 #define SARTC_BASE		0x90010000	/* Real-Time Clock */
     37 #define SAPMR_BASE		0x90020000	/* Power Manager */
     38 #define SARCR_BASE		0x90030000	/* Reset Controller */
     39 #define SAGPIO_BASE		0x90040000	/* GPIO */
     40 #define SAIPIC_BASE		0x90050000	/* Interrupt Controller */
     41 #define SAPPC_BASE		0x90060000	/* Peripheral Pin Controller */
     42 #define SAUDC_BASE		0x80000000	/* USB Device Controller*/
     43 #define SACOM1_BASE		0x80010000	/* GPCLK/UART 1 */
     44 #define SACOM2_BASE		0x80030000	/* Infrared Comm. Port (ICP) */
     45 #define SACOM3_BASE		0x80050000	/* UART 3  */
     46 #define SAMCP_BASE		0x80060000	/* MCP Controller */
     47 #define SASSP_BASE		0x80070000	/* Synchronous serial port */
     48 
     49 #define SADMAC_BASE		0xB0000000	/* DMA Controller */
     50 #define SALCD_BASE		0xB0100000	/* LCD */
     51 
     52 /* Register base virtual addresses mapped by initarm() */
     53 #define SACOM3_VBASE		0xd000d000
     54 
     55 /* Interrupt controller registers */
     56 #define SAIPIC_NPORTS		9
     57 #define SAIPIC_IP		0x00		/* IRQ pending register */
     58 #define SAIPIC_MR		0x04		/* Mask register */
     59 #define SAIPIC_LR		0x08		/* Level register */
     60 #define SAIPIC_FP		0x10		/* FIQ pending register */
     61 #define SAIPIC_PR		0x20		/* Pending register */
     62 #define SAIPIC_CR		0x0C		/* Control register */
     63 
     64 /* width of interrupt controller */
     65 #define ICU_LEN			32
     66 
     67 /* Reset controller registers */
     68 #define SARCR_RSRR		0x0		/* Software reset register */
     69 #define SARCR_RCSR		0x4		/* Reset status register */
     70 #define SARCR_TUCR		0x8		/* Test Unit control reg */
     71 
     72 #endif /* _ARM_SA11X0_REG_H_ */
     73