1 /* $NetBSD: sa11x0_dmacreg.h,v 1.3 2008/04/28 20:23:14 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, The NetBSD Foundation, Inc. All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by IWAMOTO Toshihiro. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* SA11[01]0 integrated DMA controller */ 32 33 #define SADMAC_NPORTS 40 34 35 #define SADMAC_DAR0 0x00 /* DMA device address register */ 36 #define SADMAC_DCR0_SET 0x04 /* DMA control/status (set) */ 37 #define SADMAC_DCR0_CLR 0x08 /* DMA control/status (clear) */ 38 #define SADMAC_DCR0 0x0C /* DMA control/status (read only) */ 39 #define SADMAC_DBSA0 0x10 /* DMA Buffer A start address */ 40 #define SADMAC_DBTA0 0x14 /* DMA Buffer A transfer count */ 41 #define SADMAC_DBSB0 0x18 /* DMA Buffer B start address */ 42 #define SADMAC_DBTB0 0x1C /* DMA Buffer B transfer count */ 43 44 #define SADMAC_DAR1 0x20 45 #define SADMAC_DCR1_SET 0x24 46 #define SADMAC_DCR1_CLR 0x28 47 #define SADMAC_DCR1 0x2C 48 #define SADMAC_DBSA1 0x30 49 #define SADMAC_DBTA1 0x34 50 #define SADMAC_DBSB1 0x38 51 #define SADMAC_DBTB1 0x3C 52 53 #define SADMAC_DAR2 0x40 54 #define SADMAC_DCR2_SET 0x44 55 #define SADMAC_DCR2_CLR 0x48 56 #define SADMAC_DCR2 0x4C 57 #define SADMAC_DBSA2 0x50 58 #define SADMAC_DBTA2 0x54 59 #define SADMAC_DBSB2 0x58 60 #define SADMAC_DBTB2 0x5C 61 62 #define SADMAC_DAR3 0x60 63 #define SADMAC_DCR3_SET 0x64 64 #define SADMAC_DCR3_CLR 0x68 65 #define SADMAC_DCR3 0x6C 66 #define SADMAC_DBSA3 0x70 67 #define SADMAC_DBTA3 0x74 68 #define SADMAC_DBSB3 0x78 69 #define SADMAC_DBTB3 0x7C 70 71 #define SADMAC_DAR4 0x80 72 #define SADMAC_DCR4_SET 0x84 73 #define SADMAC_DCR4_CLR 0x88 74 #define SADMAC_DCR4 0x8C 75 #define SADMAC_DBSA4 0x90 76 #define SADMAC_DBTA4 0x94 77 #define SADMAC_DBSB4 0x98 78 #define SADMAC_DBTB4 0x9C 79 80 #define SADMAC_DAR5 0xA0 81 #define SADMAC_DCR5_SET 0xA4 82 #define SADMAC_DCR5_CLR 0xA8 83 #define SADMAC_DCR5 0xAC 84 #define SADMAC_DBSA5 0xB0 85 #define SADMAC_DBTA5 0xB4 86 #define SADMAC_DBSB5 0xB8 87 #define SADMAC_DBTB5 0xBC 88
Indexes created Sat Sep 20 22:09:52 GMT 2025