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      1 /*	$NetBSD: imx_ahcisatareg.h,v 1.2 2024/02/07 04:20:27 msaitoh Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2014 Ryo Shimizu
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     18  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     19  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
     20  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     22  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
     24  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
     25  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     26  * POSSIBILITY OF SUCH DAMAGE.
     27  */
     28 
     29 #ifndef _ARM_NXP_IMX_AHCISATAREG_H_
     30 #define _ARM_NXP_IMX_AHCISATAREG_H_
     31 
     32 #define SATA_CAP				0x00000000
     33 #define  SATA_CAP_SSS				__BIT(27)
     34 #define SATA_PI					0x0000000c
     35 #define  SATA_PI_PI				__BIT(0)
     36 #define SATA_BISTAFR				0x000000a0
     37 #define SATA_BISTCR				0x000000a4
     38 #define SATA_BISTFCTR				0x000000a8
     39 #define SATA_BISTSR				0x000000ac
     40 #define SATA_OOBR				0x000000bc
     41 #define SATA_GPCR				0x000000d0
     42 #define SATA_GPSR				0x000000d4
     43 #define SATA_TIMER1MS				0x000000e0
     44 #define SATA_TESTR				0x000000f4
     45 #define SATA_VERSIONR				0x000000f8
     46 
     47 #define SATA_P0DMACR				0x00000170
     48 #define  SATA_P0DMACR_RXTS(n)			__SHIFTIN(n, __BITS(7, 4))
     49 #define  SATA_P0DMACR_TXTS(n)			__SHIFTIN(n, __BITS(3, 0))
     50 #define SATA_P0PHYCR				0x00000178
     51 #define  SATA_P0PHYCR_CR_READ			__BIT(19)
     52 #define  SATA_P0PHYCR_CR_WRITE			__BIT(18)
     53 #define  SATA_P0PHYCR_CR_CAP_DATA		__BIT(17)
     54 #define  SATA_P0PHYCR_CR_CAP_ADDR		__BIT(16)
     55 #define  SATA_P0PHYCR_CR_DATA_IN(v)		((v) & 0xffff)
     56 #define SATA_P0PHYSR				0x0000017c
     57 #define  SATA_P0PHYSR_CR_ACK			__BIT(18)
     58 #define  SATA_P0PHYSR_CR_DATA_OUT(v)		((v) & 0xffff)
     59 
     60 /* phy registers */
     61 #define SATA_PHY_CLOCK_CTL_OVRD			0x0013
     62 #define SATA_PHY_CLOCK_CTL_OVRD_MPLL_PWRON	__BIT(2)
     63 
     64 #define SATA_PHY_CLOCK_RESET			0x7f3f
     65 #define SATA_PHY_CLOCK_RESET_RST		__BIT(0)
     66 
     67 #define SATA_PHY_LANE0_OUT_STAT			0x2003
     68 #define SATA_PHY_LANE0_OUT_STAT_RX_PLL_STATE	__BIT(1)
     69 
     70 #define SATA_PHY_LANE0_TX_OVRD			0x2004
     71 #define SATA_PHY_LANE0_TX_OVRD_TX_EN(n)		__SHIFTIN(n, __BITS(3, 1))
     72 #define SATA_PHY_LANE0_RX_OVRD			0x2005
     73 #define SATA_PHY_LANE0_RX_OVRD_RX_EN		__BIT(2)
     74 #define SATA_PHY_LANE0_RX_OVRD_RX_PLL_PWRON	__BIT(1)
     75 
     76 #endif /* _ARM_NXP_IMX_AHCISATAREG_H_ */
     77