1 #ifndef ADRENO_PM4_XML 2 #define ADRENO_PM4_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13) 12 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13) 13 - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 79608 bytes, from 2019-01-21 14:36:17) 14 - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2018-12-05 15:25:53) 15 - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43155 bytes, from 2019-05-03 18:24:29) 16 - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13) 17 - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13) 18 - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2019-05-03 18:24:29) 19 - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 148461 bytes, from 2019-05-03 18:24:37) 20 - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07) 21 - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13) 22 23 Copyright (C) 2013-2019 by the following authors: 24 - Rob Clark <robdclark (at) gmail.com> (robclark) 25 - Ilia Mirkin <imirkin (at) alum.mit.edu> (imirkin) 26 27 Permission is hereby granted, free of charge, to any person obtaining 28 a copy of this software and associated documentation files (the 29 "Software"), to deal in the Software without restriction, including 30 without limitation the rights to use, copy, modify, merge, publish, 31 distribute, sublicense, and/or sell copies of the Software, and to 32 permit persons to whom the Software is furnished to do so, subject to 33 the following conditions: 34 35 The above copyright notice and this permission notice (including the 36 next paragraph) shall be included in all copies or substantial 37 portions of the Software. 38 39 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 40 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 41 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 42 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 43 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 44 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 45 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48 49 enum vgt_event_type { 50 VS_DEALLOC = 0, 51 PS_DEALLOC = 1, 52 VS_DONE_TS = 2, 53 PS_DONE_TS = 3, 54 CACHE_FLUSH_TS = 4, 55 CONTEXT_DONE = 5, 56 CACHE_FLUSH = 6, 57 HLSQ_FLUSH = 7, 58 VIZQUERY_START = 7, 59 VIZQUERY_END = 8, 60 SC_WAIT_WC = 9, 61 RST_PIX_CNT = 13, 62 RST_VTX_CNT = 14, 63 TILE_FLUSH = 15, 64 STAT_EVENT = 16, 65 CACHE_FLUSH_AND_INV_TS_EVENT = 20, 66 ZPASS_DONE = 21, 67 CACHE_FLUSH_AND_INV_EVENT = 22, 68 PERFCOUNTER_START = 23, 69 PERFCOUNTER_STOP = 24, 70 VS_FETCH_DONE = 27, 71 FACENESS_FLUSH = 28, 72 FLUSH_SO_0 = 17, 73 FLUSH_SO_1 = 18, 74 FLUSH_SO_2 = 19, 75 FLUSH_SO_3 = 20, 76 PC_CCU_INVALIDATE_DEPTH = 24, 77 PC_CCU_INVALIDATE_COLOR = 25, 78 UNK_1C = 28, 79 UNK_1D = 29, 80 BLIT = 30, 81 UNK_25 = 37, 82 LRZ_FLUSH = 38, 83 UNK_2C = 44, 84 UNK_2D = 45, 85 }; 86 87 enum pc_di_primtype { 88 DI_PT_NONE = 0, 89 DI_PT_POINTLIST_PSIZE = 1, 90 DI_PT_LINELIST = 2, 91 DI_PT_LINESTRIP = 3, 92 DI_PT_TRILIST = 4, 93 DI_PT_TRIFAN = 5, 94 DI_PT_TRISTRIP = 6, 95 DI_PT_LINELOOP = 7, 96 DI_PT_RECTLIST = 8, 97 DI_PT_POINTLIST = 9, 98 DI_PT_LINE_ADJ = 10, 99 DI_PT_LINESTRIP_ADJ = 11, 100 DI_PT_TRI_ADJ = 12, 101 DI_PT_TRISTRIP_ADJ = 13, 102 }; 103 104 enum pc_di_src_sel { 105 DI_SRC_SEL_DMA = 0, 106 DI_SRC_SEL_IMMEDIATE = 1, 107 DI_SRC_SEL_AUTO_INDEX = 2, 108 DI_SRC_SEL_RESERVED = 3, 109 }; 110 111 enum pc_di_face_cull_sel { 112 DI_FACE_CULL_NONE = 0, 113 DI_FACE_CULL_FETCH = 1, 114 DI_FACE_BACKFACE_CULL = 2, 115 DI_FACE_FRONTFACE_CULL = 3, 116 }; 117 118 enum pc_di_index_size { 119 INDEX_SIZE_IGN = 0, 120 INDEX_SIZE_16_BIT = 0, 121 INDEX_SIZE_32_BIT = 1, 122 INDEX_SIZE_8_BIT = 2, 123 INDEX_SIZE_INVALID = 0, 124 }; 125 126 enum pc_di_vis_cull_mode { 127 IGNORE_VISIBILITY = 0, 128 USE_VISIBILITY = 1, 129 }; 130 131 enum adreno_pm4_packet_type { 132 CP_TYPE0_PKT = 0, 133 CP_TYPE1_PKT = 0x40000000, 134 CP_TYPE2_PKT = 0x80000000, 135 CP_TYPE3_PKT = 0xc0000000, 136 CP_TYPE4_PKT = 0x40000000, 137 CP_TYPE7_PKT = 0x70000000, 138 }; 139 140 enum adreno_pm4_type3_packets { 141 CP_ME_INIT = 72, 142 CP_NOP = 16, 143 CP_PREEMPT_ENABLE = 28, 144 CP_PREEMPT_TOKEN = 30, 145 CP_INDIRECT_BUFFER = 63, 146 CP_INDIRECT_BUFFER_PFD = 55, 147 CP_WAIT_FOR_IDLE = 38, 148 CP_WAIT_REG_MEM = 60, 149 CP_WAIT_REG_EQ = 82, 150 CP_WAIT_REG_GTE = 83, 151 CP_WAIT_UNTIL_READ = 92, 152 CP_WAIT_IB_PFD_COMPLETE = 93, 153 CP_REG_RMW = 33, 154 CP_SET_BIN_DATA = 47, 155 CP_SET_BIN_DATA5 = 47, 156 CP_REG_TO_MEM = 62, 157 CP_MEM_WRITE = 61, 158 CP_MEM_WRITE_CNTR = 79, 159 CP_COND_EXEC = 68, 160 CP_COND_WRITE = 69, 161 CP_COND_WRITE5 = 69, 162 CP_EVENT_WRITE = 70, 163 CP_EVENT_WRITE_SHD = 88, 164 CP_EVENT_WRITE_CFL = 89, 165 CP_EVENT_WRITE_ZPD = 91, 166 CP_RUN_OPENCL = 49, 167 CP_DRAW_INDX = 34, 168 CP_DRAW_INDX_2 = 54, 169 CP_DRAW_INDX_BIN = 52, 170 CP_DRAW_INDX_2_BIN = 53, 171 CP_VIZ_QUERY = 35, 172 CP_SET_STATE = 37, 173 CP_SET_CONSTANT = 45, 174 CP_IM_LOAD = 39, 175 CP_IM_LOAD_IMMEDIATE = 43, 176 CP_LOAD_CONSTANT_CONTEXT = 46, 177 CP_INVALIDATE_STATE = 59, 178 CP_SET_SHADER_BASES = 74, 179 CP_SET_BIN_MASK = 80, 180 CP_SET_BIN_SELECT = 81, 181 CP_CONTEXT_UPDATE = 94, 182 CP_INTERRUPT = 64, 183 CP_IM_STORE = 44, 184 CP_SET_DRAW_INIT_FLAGS = 75, 185 CP_SET_PROTECTED_MODE = 95, 186 CP_BOOTSTRAP_UCODE = 111, 187 CP_LOAD_STATE = 48, 188 CP_LOAD_STATE4 = 48, 189 CP_COND_INDIRECT_BUFFER_PFE = 58, 190 CP_COND_INDIRECT_BUFFER_PFD = 50, 191 CP_INDIRECT_BUFFER_PFE = 63, 192 CP_SET_BIN = 76, 193 CP_TEST_TWO_MEMS = 113, 194 CP_REG_WR_NO_CTXT = 120, 195 CP_RECORD_PFP_TIMESTAMP = 17, 196 CP_SET_SECURE_MODE = 102, 197 CP_WAIT_FOR_ME = 19, 198 CP_SET_DRAW_STATE = 67, 199 CP_DRAW_INDX_OFFSET = 56, 200 CP_DRAW_INDIRECT = 40, 201 CP_DRAW_INDX_INDIRECT = 41, 202 CP_DRAW_AUTO = 36, 203 CP_UNKNOWN_19 = 25, 204 CP_UNKNOWN_1A = 26, 205 CP_UNKNOWN_4E = 78, 206 CP_WIDE_REG_WRITE = 116, 207 CP_SCRATCH_TO_REG = 77, 208 CP_REG_TO_SCRATCH = 74, 209 CP_WAIT_MEM_WRITES = 18, 210 CP_COND_REG_EXEC = 71, 211 CP_MEM_TO_REG = 66, 212 CP_EXEC_CS_INDIRECT = 65, 213 CP_EXEC_CS = 51, 214 CP_PERFCOUNTER_ACTION = 80, 215 CP_SMMU_TABLE_UPDATE = 83, 216 CP_SET_MARKER = 101, 217 CP_SET_PSEUDO_REG = 86, 218 CP_CONTEXT_REG_BUNCH = 92, 219 CP_YIELD_ENABLE = 28, 220 CP_SKIP_IB2_ENABLE_GLOBAL = 29, 221 CP_SKIP_IB2_ENABLE_LOCAL = 35, 222 CP_SET_SUBDRAW_SIZE = 53, 223 CP_SET_VISIBILITY_OVERRIDE = 100, 224 CP_PREEMPT_ENABLE_GLOBAL = 105, 225 CP_PREEMPT_ENABLE_LOCAL = 106, 226 CP_CONTEXT_SWITCH_YIELD = 107, 227 CP_SET_RENDER_MODE = 108, 228 CP_COMPUTE_CHECKPOINT = 110, 229 CP_MEM_TO_MEM = 115, 230 CP_BLIT = 44, 231 CP_REG_TEST = 57, 232 CP_SET_MODE = 99, 233 CP_LOAD_STATE6_GEOM = 50, 234 CP_LOAD_STATE6_FRAG = 52, 235 CP_LOAD_STATE6 = 54, 236 IN_IB_PREFETCH_END = 23, 237 IN_SUBBLK_PREFETCH = 31, 238 IN_INSTR_PREFETCH = 32, 239 IN_INSTR_MATCH = 71, 240 IN_CONST_PREFETCH = 73, 241 IN_INCR_UPDT_STATE = 85, 242 IN_INCR_UPDT_CONST = 86, 243 IN_INCR_UPDT_INSTR = 87, 244 PKT4 = 4, 245 CP_UNK_A6XX_14 = 20, 246 CP_UNK_A6XX_55 = 85, 247 CP_REG_WRITE = 109, 248 }; 249 250 enum adreno_state_block { 251 SB_VERT_TEX = 0, 252 SB_VERT_MIPADDR = 1, 253 SB_FRAG_TEX = 2, 254 SB_FRAG_MIPADDR = 3, 255 SB_VERT_SHADER = 4, 256 SB_GEOM_SHADER = 5, 257 SB_FRAG_SHADER = 6, 258 SB_COMPUTE_SHADER = 7, 259 }; 260 261 enum adreno_state_type { 262 ST_SHADER = 0, 263 ST_CONSTANTS = 1, 264 }; 265 266 enum adreno_state_src { 267 SS_DIRECT = 0, 268 SS_INVALID_ALL_IC = 2, 269 SS_INVALID_PART_IC = 3, 270 SS_INDIRECT = 4, 271 SS_INDIRECT_TCM = 5, 272 SS_INDIRECT_STM = 6, 273 }; 274 275 enum a4xx_state_block { 276 SB4_VS_TEX = 0, 277 SB4_HS_TEX = 1, 278 SB4_DS_TEX = 2, 279 SB4_GS_TEX = 3, 280 SB4_FS_TEX = 4, 281 SB4_CS_TEX = 5, 282 SB4_VS_SHADER = 8, 283 SB4_HS_SHADER = 9, 284 SB4_DS_SHADER = 10, 285 SB4_GS_SHADER = 11, 286 SB4_FS_SHADER = 12, 287 SB4_CS_SHADER = 13, 288 SB4_SSBO = 14, 289 SB4_CS_SSBO = 15, 290 }; 291 292 enum a4xx_state_type { 293 ST4_SHADER = 0, 294 ST4_CONSTANTS = 1, 295 }; 296 297 enum a4xx_state_src { 298 SS4_DIRECT = 0, 299 SS4_INDIRECT = 2, 300 }; 301 302 enum a6xx_state_block { 303 SB6_VS_TEX = 0, 304 SB6_HS_TEX = 1, 305 SB6_DS_TEX = 2, 306 SB6_GS_TEX = 3, 307 SB6_FS_TEX = 4, 308 SB6_CS_TEX = 5, 309 SB6_VS_SHADER = 8, 310 SB6_HS_SHADER = 9, 311 SB6_DS_SHADER = 10, 312 SB6_GS_SHADER = 11, 313 SB6_FS_SHADER = 12, 314 SB6_CS_SHADER = 13, 315 SB6_IBO = 14, 316 SB6_CS_IBO = 15, 317 }; 318 319 enum a6xx_state_type { 320 ST6_SHADER = 0, 321 ST6_CONSTANTS = 1, 322 ST6_IBO = 3, 323 }; 324 325 enum a6xx_state_src { 326 SS6_DIRECT = 0, 327 SS6_INDIRECT = 2, 328 }; 329 330 enum a4xx_index_size { 331 INDEX4_SIZE_8_BIT = 0, 332 INDEX4_SIZE_16_BIT = 1, 333 INDEX4_SIZE_32_BIT = 2, 334 }; 335 336 enum cp_cond_function { 337 WRITE_ALWAYS = 0, 338 WRITE_LT = 1, 339 WRITE_LE = 2, 340 WRITE_EQ = 3, 341 WRITE_NE = 4, 342 WRITE_GE = 5, 343 WRITE_GT = 6, 344 }; 345 346 enum render_mode_cmd { 347 BYPASS = 1, 348 BINNING = 2, 349 GMEM = 3, 350 BLIT2D = 5, 351 BLIT2DSCALE = 7, 352 END2D = 8, 353 }; 354 355 enum cp_blit_cmd { 356 BLIT_OP_FILL = 0, 357 BLIT_OP_COPY = 1, 358 BLIT_OP_SCALE = 3, 359 }; 360 361 enum a6xx_render_mode { 362 RM6_BYPASS = 1, 363 RM6_BINNING = 2, 364 RM6_GMEM = 4, 365 RM6_BLIT2D = 5, 366 RM6_RESOLVE = 6, 367 RM6_BLIT2DSCALE = 12, 368 }; 369 370 enum pseudo_reg { 371 SMMU_INFO = 0, 372 NON_SECURE_SAVE_ADDR = 1, 373 SECURE_SAVE_ADDR = 2, 374 NON_PRIV_SAVE_ADDR = 3, 375 COUNTER = 4, 376 }; 377 378 #define REG_CP_LOAD_STATE_0 0x00000000 379 #define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff 380 #define CP_LOAD_STATE_0_DST_OFF__SHIFT 0 381 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) 382 { 383 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK; 384 } 385 #define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000 386 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT 16 387 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) 388 { 389 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK; 390 } 391 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000 392 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT 19 393 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) 394 { 395 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK; 396 } 397 #define CP_LOAD_STATE_0_NUM_UNIT__MASK 0xffc00000 398 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22 399 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) 400 { 401 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK; 402 } 403 404 #define REG_CP_LOAD_STATE_1 0x00000001 405 #define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003 406 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0 407 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) 408 { 409 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK; 410 } 411 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc 412 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2 413 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val) 414 { 415 assert(!(val & 0x3)); 416 return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK; 417 } 418 419 #define REG_CP_LOAD_STATE4_0 0x00000000 420 #define CP_LOAD_STATE4_0_DST_OFF__MASK 0x00003fff 421 #define CP_LOAD_STATE4_0_DST_OFF__SHIFT 0 422 static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val) 423 { 424 return ((val) << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK; 425 } 426 #define CP_LOAD_STATE4_0_STATE_SRC__MASK 0x00030000 427 #define CP_LOAD_STATE4_0_STATE_SRC__SHIFT 16 428 static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val) 429 { 430 return ((val) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK; 431 } 432 #define CP_LOAD_STATE4_0_STATE_BLOCK__MASK 0x003c0000 433 #define CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT 18 434 static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val) 435 { 436 return ((val) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK; 437 } 438 #define CP_LOAD_STATE4_0_NUM_UNIT__MASK 0xffc00000 439 #define CP_LOAD_STATE4_0_NUM_UNIT__SHIFT 22 440 static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val) 441 { 442 return ((val) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK; 443 } 444 445 #define REG_CP_LOAD_STATE4_1 0x00000001 446 #define CP_LOAD_STATE4_1_STATE_TYPE__MASK 0x00000003 447 #define CP_LOAD_STATE4_1_STATE_TYPE__SHIFT 0 448 static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val) 449 { 450 return ((val) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK; 451 } 452 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK 0xfffffffc 453 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT 2 454 static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val) 455 { 456 assert(!(val & 0x3)); 457 return ((val >> 2) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK; 458 } 459 460 #define REG_CP_LOAD_STATE4_2 0x00000002 461 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK 0xffffffff 462 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT 0 463 static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val) 464 { 465 return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK; 466 } 467 468 #define REG_CP_LOAD_STATE6_0 0x00000000 469 #define CP_LOAD_STATE6_0_DST_OFF__MASK 0x00003fff 470 #define CP_LOAD_STATE6_0_DST_OFF__SHIFT 0 471 static inline uint32_t CP_LOAD_STATE6_0_DST_OFF(uint32_t val) 472 { 473 return ((val) << CP_LOAD_STATE6_0_DST_OFF__SHIFT) & CP_LOAD_STATE6_0_DST_OFF__MASK; 474 } 475 #define CP_LOAD_STATE6_0_STATE_TYPE__MASK 0x0000c000 476 #define CP_LOAD_STATE6_0_STATE_TYPE__SHIFT 14 477 static inline uint32_t CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val) 478 { 479 return ((val) << CP_LOAD_STATE6_0_STATE_TYPE__SHIFT) & CP_LOAD_STATE6_0_STATE_TYPE__MASK; 480 } 481 #define CP_LOAD_STATE6_0_STATE_SRC__MASK 0x00030000 482 #define CP_LOAD_STATE6_0_STATE_SRC__SHIFT 16 483 static inline uint32_t CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val) 484 { 485 return ((val) << CP_LOAD_STATE6_0_STATE_SRC__SHIFT) & CP_LOAD_STATE6_0_STATE_SRC__MASK; 486 } 487 #define CP_LOAD_STATE6_0_STATE_BLOCK__MASK 0x003c0000 488 #define CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT 18 489 static inline uint32_t CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val) 490 { 491 return ((val) << CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE6_0_STATE_BLOCK__MASK; 492 } 493 #define CP_LOAD_STATE6_0_NUM_UNIT__MASK 0xffc00000 494 #define CP_LOAD_STATE6_0_NUM_UNIT__SHIFT 22 495 static inline uint32_t CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val) 496 { 497 return ((val) << CP_LOAD_STATE6_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE6_0_NUM_UNIT__MASK; 498 } 499 500 #define REG_CP_LOAD_STATE6_1 0x00000001 501 #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK 0xfffffffc 502 #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT 2 503 static inline uint32_t CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val) 504 { 505 assert(!(val & 0x3)); 506 return ((val >> 2) << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK; 507 } 508 509 #define REG_CP_LOAD_STATE6_2 0x00000002 510 #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK 0xffffffff 511 #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT 0 512 static inline uint32_t CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val) 513 { 514 return ((val) << CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK; 515 } 516 517 #define REG_CP_DRAW_INDX_0 0x00000000 518 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff 519 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0 520 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val) 521 { 522 return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK; 523 } 524 525 #define REG_CP_DRAW_INDX_1 0x00000001 526 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f 527 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0 528 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val) 529 { 530 return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK; 531 } 532 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0 533 #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT 6 534 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val) 535 { 536 return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK; 537 } 538 #define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600 539 #define CP_DRAW_INDX_1_VIS_CULL__SHIFT 9 540 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val) 541 { 542 return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK; 543 } 544 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800 545 #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT 11 546 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val) 547 { 548 return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK; 549 } 550 #define CP_DRAW_INDX_1_NOT_EOP 0x00001000 551 #define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000 552 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000 553 #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK 0xff000000 554 #define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT 24 555 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val) 556 { 557 return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK; 558 } 559 560 #define REG_CP_DRAW_INDX_2 0x00000002 561 #define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff 562 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0 563 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val) 564 { 565 return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK; 566 } 567 568 #define REG_CP_DRAW_INDX_3 0x00000003 569 #define CP_DRAW_INDX_3_INDX_BASE__MASK 0xffffffff 570 #define CP_DRAW_INDX_3_INDX_BASE__SHIFT 0 571 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val) 572 { 573 return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK; 574 } 575 576 #define REG_CP_DRAW_INDX_4 0x00000004 577 #define CP_DRAW_INDX_4_INDX_SIZE__MASK 0xffffffff 578 #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT 0 579 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val) 580 { 581 return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK; 582 } 583 584 #define REG_CP_DRAW_INDX_2_0 0x00000000 585 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff 586 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0 587 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val) 588 { 589 return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK; 590 } 591 592 #define REG_CP_DRAW_INDX_2_1 0x00000001 593 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f 594 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0 595 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val) 596 { 597 return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK; 598 } 599 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0 600 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT 6 601 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val) 602 { 603 return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK; 604 } 605 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600 606 #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT 9 607 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val) 608 { 609 return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK; 610 } 611 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800 612 #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT 11 613 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val) 614 { 615 return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK; 616 } 617 #define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000 618 #define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000 619 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000 620 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK 0xff000000 621 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT 24 622 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val) 623 { 624 return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK; 625 } 626 627 #define REG_CP_DRAW_INDX_2_2 0x00000002 628 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff 629 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0 630 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val) 631 { 632 return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK; 633 } 634 635 #define REG_CP_DRAW_INDX_OFFSET_0 0x00000000 636 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK 0x0000003f 637 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT 0 638 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val) 639 { 640 return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK; 641 } 642 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK 0x000000c0 643 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT 6 644 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val) 645 { 646 return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK; 647 } 648 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000300 649 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT 8 650 static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val) 651 { 652 return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK; 653 } 654 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00 655 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10 656 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val) 657 { 658 return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK; 659 } 660 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK 0x01f00000 661 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT 20 662 static inline uint32_t CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val) 663 { 664 return ((val) << CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT) & CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK; 665 } 666 667 #define REG_CP_DRAW_INDX_OFFSET_1 0x00000001 668 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK 0xffffffff 669 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT 0 670 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val) 671 { 672 return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK; 673 } 674 675 #define REG_CP_DRAW_INDX_OFFSET_2 0x00000002 676 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK 0xffffffff 677 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT 0 678 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val) 679 { 680 return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK; 681 } 682 683 #define REG_CP_DRAW_INDX_OFFSET_3 0x00000003 684 685 #define REG_CP_DRAW_INDX_OFFSET_4 0x00000004 686 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK 0xffffffff 687 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT 0 688 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val) 689 { 690 return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK; 691 } 692 693 #define REG_CP_DRAW_INDX_OFFSET_5 0x00000005 694 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK 0xffffffff 695 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT 0 696 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val) 697 { 698 return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK; 699 } 700 701 #define REG_A4XX_CP_DRAW_INDIRECT_0 0x00000000 702 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f 703 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT 0 704 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val) 705 { 706 return ((val) << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK; 707 } 708 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0 709 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT 6 710 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val) 711 { 712 return ((val) << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK; 713 } 714 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK 0x00000300 715 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT 8 716 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val) 717 { 718 return ((val) << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK; 719 } 720 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00 721 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT 10 722 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val) 723 { 724 return ((val) << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK; 725 } 726 #define A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__MASK 0x01f00000 727 #define A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT 20 728 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_TESS_MODE(uint32_t val) 729 { 730 return ((val) << A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__MASK; 731 } 732 733 #define REG_A4XX_CP_DRAW_INDIRECT_1 0x00000001 734 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK 0xffffffff 735 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT 0 736 static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val) 737 { 738 return ((val) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK; 739 } 740 741 742 #define REG_A5XX_CP_DRAW_INDIRECT_2 0x00000002 743 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK 0xffffffff 744 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT 0 745 static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val) 746 { 747 return ((val) << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK; 748 } 749 750 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_0 0x00000000 751 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f 752 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT 0 753 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val) 754 { 755 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK; 756 } 757 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0 758 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT 6 759 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val) 760 { 761 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK; 762 } 763 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK 0x00000300 764 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT 8 765 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val) 766 { 767 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK; 768 } 769 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00 770 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT 10 771 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val) 772 { 773 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK; 774 } 775 #define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK 0x01f00000 776 #define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT 20 777 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE(uint32_t val) 778 { 779 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK; 780 } 781 782 783 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_1 0x00000001 784 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK 0xffffffff 785 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT 0 786 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val) 787 { 788 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK; 789 } 790 791 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_2 0x00000002 792 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK 0xffffffff 793 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT 0 794 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val) 795 { 796 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK; 797 } 798 799 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_3 0x00000003 800 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK 0xffffffff 801 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT 0 802 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val) 803 { 804 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK; 805 } 806 807 808 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_1 0x00000001 809 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK 0xffffffff 810 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT 0 811 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val) 812 { 813 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK; 814 } 815 816 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_2 0x00000002 817 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK 0xffffffff 818 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT 0 819 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val) 820 { 821 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK; 822 } 823 824 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_3 0x00000003 825 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK 0xffffffff 826 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT 0 827 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val) 828 { 829 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK; 830 } 831 832 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_4 0x00000004 833 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK 0xffffffff 834 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT 0 835 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val) 836 { 837 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK; 838 } 839 840 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_5 0x00000005 841 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK 0xffffffff 842 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT 0 843 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val) 844 { 845 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK; 846 } 847 848 static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; } 849 850 static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; } 851 #define CP_SET_DRAW_STATE__0_COUNT__MASK 0x0000ffff 852 #define CP_SET_DRAW_STATE__0_COUNT__SHIFT 0 853 static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val) 854 { 855 return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK; 856 } 857 #define CP_SET_DRAW_STATE__0_DIRTY 0x00010000 858 #define CP_SET_DRAW_STATE__0_DISABLE 0x00020000 859 #define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS 0x00040000 860 #define CP_SET_DRAW_STATE__0_LOAD_IMMED 0x00080000 861 #define CP_SET_DRAW_STATE__0_ENABLE_MASK__MASK 0x00f00000 862 #define CP_SET_DRAW_STATE__0_ENABLE_MASK__SHIFT 20 863 static inline uint32_t CP_SET_DRAW_STATE__0_ENABLE_MASK(uint32_t val) 864 { 865 return ((val) << CP_SET_DRAW_STATE__0_ENABLE_MASK__SHIFT) & CP_SET_DRAW_STATE__0_ENABLE_MASK__MASK; 866 } 867 #define CP_SET_DRAW_STATE__0_GROUP_ID__MASK 0x1f000000 868 #define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT 24 869 static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val) 870 { 871 return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK; 872 } 873 874 static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; } 875 #define CP_SET_DRAW_STATE__1_ADDR_LO__MASK 0xffffffff 876 #define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT 0 877 static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val) 878 { 879 return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK; 880 } 881 882 static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; } 883 #define CP_SET_DRAW_STATE__2_ADDR_HI__MASK 0xffffffff 884 #define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT 0 885 static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val) 886 { 887 return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK; 888 } 889 890 #define REG_CP_SET_BIN_0 0x00000000 891 892 #define REG_CP_SET_BIN_1 0x00000001 893 #define CP_SET_BIN_1_X1__MASK 0x0000ffff 894 #define CP_SET_BIN_1_X1__SHIFT 0 895 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val) 896 { 897 return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK; 898 } 899 #define CP_SET_BIN_1_Y1__MASK 0xffff0000 900 #define CP_SET_BIN_1_Y1__SHIFT 16 901 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val) 902 { 903 return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK; 904 } 905 906 #define REG_CP_SET_BIN_2 0x00000002 907 #define CP_SET_BIN_2_X2__MASK 0x0000ffff 908 #define CP_SET_BIN_2_X2__SHIFT 0 909 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val) 910 { 911 return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK; 912 } 913 #define CP_SET_BIN_2_Y2__MASK 0xffff0000 914 #define CP_SET_BIN_2_Y2__SHIFT 16 915 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val) 916 { 917 return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK; 918 } 919 920 #define REG_CP_SET_BIN_DATA_0 0x00000000 921 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK 0xffffffff 922 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT 0 923 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val) 924 { 925 return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK; 926 } 927 928 #define REG_CP_SET_BIN_DATA_1 0x00000001 929 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK 0xffffffff 930 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT 0 931 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val) 932 { 933 return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK; 934 } 935 936 #define REG_CP_SET_BIN_DATA5_0 0x00000000 937 #define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK 0x003f0000 938 #define CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT 16 939 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val) 940 { 941 return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK; 942 } 943 #define CP_SET_BIN_DATA5_0_VSC_N__MASK 0x07c00000 944 #define CP_SET_BIN_DATA5_0_VSC_N__SHIFT 22 945 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val) 946 { 947 return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK; 948 } 949 950 #define REG_CP_SET_BIN_DATA5_1 0x00000001 951 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK 0xffffffff 952 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT 0 953 static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val) 954 { 955 return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK; 956 } 957 958 #define REG_CP_SET_BIN_DATA5_2 0x00000002 959 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK 0xffffffff 960 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT 0 961 static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val) 962 { 963 return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK; 964 } 965 966 #define REG_CP_SET_BIN_DATA5_3 0x00000003 967 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK 0xffffffff 968 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT 0 969 static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val) 970 { 971 return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK; 972 } 973 974 #define REG_CP_SET_BIN_DATA5_4 0x00000004 975 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK 0xffffffff 976 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT 0 977 static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val) 978 { 979 return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK; 980 } 981 982 #define REG_CP_SET_BIN_DATA5_5 0x00000005 983 #define CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__MASK 0xffffffff 984 #define CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__SHIFT 0 985 static inline uint32_t CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO(uint32_t val) 986 { 987 return ((val) << CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__SHIFT) & CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__MASK; 988 } 989 990 #define REG_CP_SET_BIN_DATA5_6 0x00000006 991 #define CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__MASK 0xffffffff 992 #define CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__SHIFT 0 993 static inline uint32_t CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO(uint32_t val) 994 { 995 return ((val) << CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__SHIFT) & CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__MASK; 996 } 997 998 #define REG_CP_REG_TO_MEM_0 0x00000000 999 #define CP_REG_TO_MEM_0_REG__MASK 0x0000ffff 1000 #define CP_REG_TO_MEM_0_REG__SHIFT 0 1001 static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val) 1002 { 1003 return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK; 1004 } 1005 #define CP_REG_TO_MEM_0_CNT__MASK 0x3ff80000 1006 #define CP_REG_TO_MEM_0_CNT__SHIFT 19 1007 static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val) 1008 { 1009 return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK; 1010 } 1011 #define CP_REG_TO_MEM_0_64B 0x40000000 1012 #define CP_REG_TO_MEM_0_ACCUMULATE 0x80000000 1013 1014 #define REG_CP_REG_TO_MEM_1 0x00000001 1015 #define CP_REG_TO_MEM_1_DEST__MASK 0xffffffff 1016 #define CP_REG_TO_MEM_1_DEST__SHIFT 0 1017 static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val) 1018 { 1019 return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK; 1020 } 1021 1022 #define REG_CP_REG_TO_MEM_2 0x00000002 1023 #define CP_REG_TO_MEM_2_DEST_HI__MASK 0xffffffff 1024 #define CP_REG_TO_MEM_2_DEST_HI__SHIFT 0 1025 static inline uint32_t CP_REG_TO_MEM_2_DEST_HI(uint32_t val) 1026 { 1027 return ((val) << CP_REG_TO_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_2_DEST_HI__MASK; 1028 } 1029 1030 #define REG_CP_MEM_TO_REG_0 0x00000000 1031 #define CP_MEM_TO_REG_0_REG__MASK 0x0000ffff 1032 #define CP_MEM_TO_REG_0_REG__SHIFT 0 1033 static inline uint32_t CP_MEM_TO_REG_0_REG(uint32_t val) 1034 { 1035 return ((val) << CP_MEM_TO_REG_0_REG__SHIFT) & CP_MEM_TO_REG_0_REG__MASK; 1036 } 1037 #define CP_MEM_TO_REG_0_CNT__MASK 0x3ff80000 1038 #define CP_MEM_TO_REG_0_CNT__SHIFT 19 1039 static inline uint32_t CP_MEM_TO_REG_0_CNT(uint32_t val) 1040 { 1041 return ((val) << CP_MEM_TO_REG_0_CNT__SHIFT) & CP_MEM_TO_REG_0_CNT__MASK; 1042 } 1043 #define CP_MEM_TO_REG_0_64B 0x40000000 1044 #define CP_MEM_TO_REG_0_ACCUMULATE 0x80000000 1045 1046 #define REG_CP_MEM_TO_REG_1 0x00000001 1047 #define CP_MEM_TO_REG_1_SRC__MASK 0xffffffff 1048 #define CP_MEM_TO_REG_1_SRC__SHIFT 0 1049 static inline uint32_t CP_MEM_TO_REG_1_SRC(uint32_t val) 1050 { 1051 return ((val) << CP_MEM_TO_REG_1_SRC__SHIFT) & CP_MEM_TO_REG_1_SRC__MASK; 1052 } 1053 1054 #define REG_CP_MEM_TO_REG_2 0x00000002 1055 #define CP_MEM_TO_REG_2_SRC_HI__MASK 0xffffffff 1056 #define CP_MEM_TO_REG_2_SRC_HI__SHIFT 0 1057 static inline uint32_t CP_MEM_TO_REG_2_SRC_HI(uint32_t val) 1058 { 1059 return ((val) << CP_MEM_TO_REG_2_SRC_HI__SHIFT) & CP_MEM_TO_REG_2_SRC_HI__MASK; 1060 } 1061 1062 #define REG_CP_MEM_TO_MEM_0 0x00000000 1063 #define CP_MEM_TO_MEM_0_NEG_A 0x00000001 1064 #define CP_MEM_TO_MEM_0_NEG_B 0x00000002 1065 #define CP_MEM_TO_MEM_0_NEG_C 0x00000004 1066 #define CP_MEM_TO_MEM_0_DOUBLE 0x20000000 1067 1068 #define REG_CP_COND_WRITE_0 0x00000000 1069 #define CP_COND_WRITE_0_FUNCTION__MASK 0x00000007 1070 #define CP_COND_WRITE_0_FUNCTION__SHIFT 0 1071 static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val) 1072 { 1073 return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK; 1074 } 1075 #define CP_COND_WRITE_0_POLL_MEMORY 0x00000010 1076 #define CP_COND_WRITE_0_WRITE_MEMORY 0x00000100 1077 1078 #define REG_CP_COND_WRITE_1 0x00000001 1079 #define CP_COND_WRITE_1_POLL_ADDR__MASK 0xffffffff 1080 #define CP_COND_WRITE_1_POLL_ADDR__SHIFT 0 1081 static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val) 1082 { 1083 return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK; 1084 } 1085 1086 #define REG_CP_COND_WRITE_2 0x00000002 1087 #define CP_COND_WRITE_2_REF__MASK 0xffffffff 1088 #define CP_COND_WRITE_2_REF__SHIFT 0 1089 static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val) 1090 { 1091 return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK; 1092 } 1093 1094 #define REG_CP_COND_WRITE_3 0x00000003 1095 #define CP_COND_WRITE_3_MASK__MASK 0xffffffff 1096 #define CP_COND_WRITE_3_MASK__SHIFT 0 1097 static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val) 1098 { 1099 return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK; 1100 } 1101 1102 #define REG_CP_COND_WRITE_4 0x00000004 1103 #define CP_COND_WRITE_4_WRITE_ADDR__MASK 0xffffffff 1104 #define CP_COND_WRITE_4_WRITE_ADDR__SHIFT 0 1105 static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val) 1106 { 1107 return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK; 1108 } 1109 1110 #define REG_CP_COND_WRITE_5 0x00000005 1111 #define CP_COND_WRITE_5_WRITE_DATA__MASK 0xffffffff 1112 #define CP_COND_WRITE_5_WRITE_DATA__SHIFT 0 1113 static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val) 1114 { 1115 return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK; 1116 } 1117 1118 #define REG_CP_COND_WRITE5_0 0x00000000 1119 #define CP_COND_WRITE5_0_FUNCTION__MASK 0x00000007 1120 #define CP_COND_WRITE5_0_FUNCTION__SHIFT 0 1121 static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val) 1122 { 1123 return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK; 1124 } 1125 #define CP_COND_WRITE5_0_POLL_MEMORY 0x00000010 1126 #define CP_COND_WRITE5_0_WRITE_MEMORY 0x00000100 1127 1128 #define REG_CP_COND_WRITE5_1 0x00000001 1129 #define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK 0xffffffff 1130 #define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT 0 1131 static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val) 1132 { 1133 return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK; 1134 } 1135 1136 #define REG_CP_COND_WRITE5_2 0x00000002 1137 #define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK 0xffffffff 1138 #define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT 0 1139 static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val) 1140 { 1141 return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK; 1142 } 1143 1144 #define REG_CP_COND_WRITE5_3 0x00000003 1145 #define CP_COND_WRITE5_3_REF__MASK 0xffffffff 1146 #define CP_COND_WRITE5_3_REF__SHIFT 0 1147 static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val) 1148 { 1149 return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK; 1150 } 1151 1152 #define REG_CP_COND_WRITE5_4 0x00000004 1153 #define CP_COND_WRITE5_4_MASK__MASK 0xffffffff 1154 #define CP_COND_WRITE5_4_MASK__SHIFT 0 1155 static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val) 1156 { 1157 return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK; 1158 } 1159 1160 #define REG_CP_COND_WRITE5_5 0x00000005 1161 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK 0xffffffff 1162 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT 0 1163 static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val) 1164 { 1165 return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK; 1166 } 1167 1168 #define REG_CP_COND_WRITE5_6 0x00000006 1169 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK 0xffffffff 1170 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT 0 1171 static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val) 1172 { 1173 return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK; 1174 } 1175 1176 #define REG_CP_COND_WRITE5_7 0x00000007 1177 #define CP_COND_WRITE5_7_WRITE_DATA__MASK 0xffffffff 1178 #define CP_COND_WRITE5_7_WRITE_DATA__SHIFT 0 1179 static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val) 1180 { 1181 return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK; 1182 } 1183 1184 #define REG_CP_DISPATCH_COMPUTE_0 0x00000000 1185 1186 #define REG_CP_DISPATCH_COMPUTE_1 0x00000001 1187 #define CP_DISPATCH_COMPUTE_1_X__MASK 0xffffffff 1188 #define CP_DISPATCH_COMPUTE_1_X__SHIFT 0 1189 static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val) 1190 { 1191 return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK; 1192 } 1193 1194 #define REG_CP_DISPATCH_COMPUTE_2 0x00000002 1195 #define CP_DISPATCH_COMPUTE_2_Y__MASK 0xffffffff 1196 #define CP_DISPATCH_COMPUTE_2_Y__SHIFT 0 1197 static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val) 1198 { 1199 return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK; 1200 } 1201 1202 #define REG_CP_DISPATCH_COMPUTE_3 0x00000003 1203 #define CP_DISPATCH_COMPUTE_3_Z__MASK 0xffffffff 1204 #define CP_DISPATCH_COMPUTE_3_Z__SHIFT 0 1205 static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val) 1206 { 1207 return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK; 1208 } 1209 1210 #define REG_CP_SET_RENDER_MODE_0 0x00000000 1211 #define CP_SET_RENDER_MODE_0_MODE__MASK 0x000001ff 1212 #define CP_SET_RENDER_MODE_0_MODE__SHIFT 0 1213 static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val) 1214 { 1215 return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK; 1216 } 1217 1218 #define REG_CP_SET_RENDER_MODE_1 0x00000001 1219 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK 0xffffffff 1220 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT 0 1221 static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val) 1222 { 1223 return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK; 1224 } 1225 1226 #define REG_CP_SET_RENDER_MODE_2 0x00000002 1227 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK 0xffffffff 1228 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT 0 1229 static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val) 1230 { 1231 return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK; 1232 } 1233 1234 #define REG_CP_SET_RENDER_MODE_3 0x00000003 1235 #define CP_SET_RENDER_MODE_3_VSC_ENABLE 0x00000008 1236 #define CP_SET_RENDER_MODE_3_GMEM_ENABLE 0x00000010 1237 1238 #define REG_CP_SET_RENDER_MODE_4 0x00000004 1239 1240 #define REG_CP_SET_RENDER_MODE_5 0x00000005 1241 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK 0xffffffff 1242 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT 0 1243 static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val) 1244 { 1245 return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK; 1246 } 1247 1248 #define REG_CP_SET_RENDER_MODE_6 0x00000006 1249 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK 0xffffffff 1250 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT 0 1251 static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val) 1252 { 1253 return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK; 1254 } 1255 1256 #define REG_CP_SET_RENDER_MODE_7 0x00000007 1257 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK 0xffffffff 1258 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT 0 1259 static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val) 1260 { 1261 return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK; 1262 } 1263 1264 #define REG_CP_COMPUTE_CHECKPOINT_0 0x00000000 1265 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK 0xffffffff 1266 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT 0 1267 static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val) 1268 { 1269 return ((val) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK; 1270 } 1271 1272 #define REG_CP_COMPUTE_CHECKPOINT_1 0x00000001 1273 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK 0xffffffff 1274 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT 0 1275 static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val) 1276 { 1277 return ((val) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK; 1278 } 1279 1280 #define REG_CP_COMPUTE_CHECKPOINT_2 0x00000002 1281 1282 #define REG_CP_COMPUTE_CHECKPOINT_3 0x00000003 1283 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK 0xffffffff 1284 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT 0 1285 static inline uint32_t CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val) 1286 { 1287 return ((val) << CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK; 1288 } 1289 1290 #define REG_CP_COMPUTE_CHECKPOINT_4 0x00000004 1291 1292 #define REG_CP_COMPUTE_CHECKPOINT_5 0x00000005 1293 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK 0xffffffff 1294 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT 0 1295 static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val) 1296 { 1297 return ((val) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK; 1298 } 1299 1300 #define REG_CP_COMPUTE_CHECKPOINT_6 0x00000006 1301 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK 0xffffffff 1302 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT 0 1303 static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val) 1304 { 1305 return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK; 1306 } 1307 1308 #define REG_CP_COMPUTE_CHECKPOINT_7 0x00000007 1309 1310 #define REG_CP_PERFCOUNTER_ACTION_0 0x00000000 1311 1312 #define REG_CP_PERFCOUNTER_ACTION_1 0x00000001 1313 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK 0xffffffff 1314 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT 0 1315 static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val) 1316 { 1317 return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK; 1318 } 1319 1320 #define REG_CP_PERFCOUNTER_ACTION_2 0x00000002 1321 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK 0xffffffff 1322 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT 0 1323 static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val) 1324 { 1325 return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK; 1326 } 1327 1328 #define REG_CP_EVENT_WRITE_0 0x00000000 1329 #define CP_EVENT_WRITE_0_EVENT__MASK 0x000000ff 1330 #define CP_EVENT_WRITE_0_EVENT__SHIFT 0 1331 static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val) 1332 { 1333 return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK; 1334 } 1335 #define CP_EVENT_WRITE_0_TIMESTAMP 0x40000000 1336 1337 #define REG_CP_EVENT_WRITE_1 0x00000001 1338 #define CP_EVENT_WRITE_1_ADDR_0_LO__MASK 0xffffffff 1339 #define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT 0 1340 static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val) 1341 { 1342 return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK; 1343 } 1344 1345 #define REG_CP_EVENT_WRITE_2 0x00000002 1346 #define CP_EVENT_WRITE_2_ADDR_0_HI__MASK 0xffffffff 1347 #define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT 0 1348 static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val) 1349 { 1350 return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK; 1351 } 1352 1353 #define REG_CP_EVENT_WRITE_3 0x00000003 1354 1355 #define REG_CP_BLIT_0 0x00000000 1356 #define CP_BLIT_0_OP__MASK 0x0000000f 1357 #define CP_BLIT_0_OP__SHIFT 0 1358 static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val) 1359 { 1360 return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK; 1361 } 1362 1363 #define REG_CP_BLIT_1 0x00000001 1364 #define CP_BLIT_1_SRC_X1__MASK 0x00003fff 1365 #define CP_BLIT_1_SRC_X1__SHIFT 0 1366 static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val) 1367 { 1368 return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK; 1369 } 1370 #define CP_BLIT_1_SRC_Y1__MASK 0x3fff0000 1371 #define CP_BLIT_1_SRC_Y1__SHIFT 16 1372 static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val) 1373 { 1374 return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK; 1375 } 1376 1377 #define REG_CP_BLIT_2 0x00000002 1378 #define CP_BLIT_2_SRC_X2__MASK 0x00003fff 1379 #define CP_BLIT_2_SRC_X2__SHIFT 0 1380 static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val) 1381 { 1382 return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK; 1383 } 1384 #define CP_BLIT_2_SRC_Y2__MASK 0x3fff0000 1385 #define CP_BLIT_2_SRC_Y2__SHIFT 16 1386 static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val) 1387 { 1388 return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK; 1389 } 1390 1391 #define REG_CP_BLIT_3 0x00000003 1392 #define CP_BLIT_3_DST_X1__MASK 0x00003fff 1393 #define CP_BLIT_3_DST_X1__SHIFT 0 1394 static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val) 1395 { 1396 return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK; 1397 } 1398 #define CP_BLIT_3_DST_Y1__MASK 0x3fff0000 1399 #define CP_BLIT_3_DST_Y1__SHIFT 16 1400 static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val) 1401 { 1402 return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK; 1403 } 1404 1405 #define REG_CP_BLIT_4 0x00000004 1406 #define CP_BLIT_4_DST_X2__MASK 0x00003fff 1407 #define CP_BLIT_4_DST_X2__SHIFT 0 1408 static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val) 1409 { 1410 return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK; 1411 } 1412 #define CP_BLIT_4_DST_Y2__MASK 0x3fff0000 1413 #define CP_BLIT_4_DST_Y2__SHIFT 16 1414 static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val) 1415 { 1416 return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK; 1417 } 1418 1419 #define REG_CP_EXEC_CS_0 0x00000000 1420 1421 #define REG_CP_EXEC_CS_1 0x00000001 1422 #define CP_EXEC_CS_1_NGROUPS_X__MASK 0xffffffff 1423 #define CP_EXEC_CS_1_NGROUPS_X__SHIFT 0 1424 static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val) 1425 { 1426 return ((val) << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK; 1427 } 1428 1429 #define REG_CP_EXEC_CS_2 0x00000002 1430 #define CP_EXEC_CS_2_NGROUPS_Y__MASK 0xffffffff 1431 #define CP_EXEC_CS_2_NGROUPS_Y__SHIFT 0 1432 static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val) 1433 { 1434 return ((val) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK; 1435 } 1436 1437 #define REG_CP_EXEC_CS_3 0x00000003 1438 #define CP_EXEC_CS_3_NGROUPS_Z__MASK 0xffffffff 1439 #define CP_EXEC_CS_3_NGROUPS_Z__SHIFT 0 1440 static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val) 1441 { 1442 return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK; 1443 } 1444 1445 #define REG_A4XX_CP_EXEC_CS_INDIRECT_0 0x00000000 1446 1447 1448 #define REG_A4XX_CP_EXEC_CS_INDIRECT_1 0x00000001 1449 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK 0xffffffff 1450 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT 0 1451 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val) 1452 { 1453 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK; 1454 } 1455 1456 #define REG_A4XX_CP_EXEC_CS_INDIRECT_2 0x00000002 1457 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK 0x00000ffc 1458 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT 2 1459 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val) 1460 { 1461 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK; 1462 } 1463 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK 0x003ff000 1464 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT 12 1465 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val) 1466 { 1467 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK; 1468 } 1469 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK 0xffc00000 1470 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT 22 1471 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val) 1472 { 1473 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK; 1474 } 1475 1476 1477 #define REG_A5XX_CP_EXEC_CS_INDIRECT_1 0x00000001 1478 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK 0xffffffff 1479 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT 0 1480 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val) 1481 { 1482 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK; 1483 } 1484 1485 #define REG_A5XX_CP_EXEC_CS_INDIRECT_2 0x00000002 1486 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK 0xffffffff 1487 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT 0 1488 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val) 1489 { 1490 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK; 1491 } 1492 1493 #define REG_A5XX_CP_EXEC_CS_INDIRECT_3 0x00000003 1494 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK 0x00000ffc 1495 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT 2 1496 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val) 1497 { 1498 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK; 1499 } 1500 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK 0x003ff000 1501 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT 12 1502 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val) 1503 { 1504 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK; 1505 } 1506 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK 0xffc00000 1507 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT 22 1508 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val) 1509 { 1510 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK; 1511 } 1512 1513 #define REG_A2XX_CP_SET_MARKER_0 0x00000000 1514 #define A2XX_CP_SET_MARKER_0_MARKER__MASK 0x0000000f 1515 #define A2XX_CP_SET_MARKER_0_MARKER__SHIFT 0 1516 static inline uint32_t A2XX_CP_SET_MARKER_0_MARKER(uint32_t val) 1517 { 1518 return ((val) << A2XX_CP_SET_MARKER_0_MARKER__SHIFT) & A2XX_CP_SET_MARKER_0_MARKER__MASK; 1519 } 1520 #define A2XX_CP_SET_MARKER_0_MODE__MASK 0x0000000f 1521 #define A2XX_CP_SET_MARKER_0_MODE__SHIFT 0 1522 static inline uint32_t A2XX_CP_SET_MARKER_0_MODE(enum a6xx_render_mode val) 1523 { 1524 return ((val) << A2XX_CP_SET_MARKER_0_MODE__SHIFT) & A2XX_CP_SET_MARKER_0_MODE__MASK; 1525 } 1526 #define A2XX_CP_SET_MARKER_0_IFPC 0x00000100 1527 1528 static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG_(uint32_t i0) { return 0x00000000 + 0x3*i0; } 1529 1530 static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; } 1531 #define A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK 0x00000007 1532 #define A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT 0 1533 static inline uint32_t A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val) 1534 { 1535 return ((val) << A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT) & A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK; 1536 } 1537 1538 static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__1(uint32_t i0) { return 0x00000001 + 0x3*i0; } 1539 #define A2XX_CP_SET_PSEUDO_REG__1_LO__MASK 0xffffffff 1540 #define A2XX_CP_SET_PSEUDO_REG__1_LO__SHIFT 0 1541 static inline uint32_t A2XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val) 1542 { 1543 return ((val) << A2XX_CP_SET_PSEUDO_REG__1_LO__SHIFT) & A2XX_CP_SET_PSEUDO_REG__1_LO__MASK; 1544 } 1545 1546 static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__2(uint32_t i0) { return 0x00000002 + 0x3*i0; } 1547 #define A2XX_CP_SET_PSEUDO_REG__2_HI__MASK 0xffffffff 1548 #define A2XX_CP_SET_PSEUDO_REG__2_HI__SHIFT 0 1549 static inline uint32_t A2XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val) 1550 { 1551 return ((val) << A2XX_CP_SET_PSEUDO_REG__2_HI__SHIFT) & A2XX_CP_SET_PSEUDO_REG__2_HI__MASK; 1552 } 1553 1554 #define REG_A2XX_CP_REG_TEST_0 0x00000000 1555 #define A2XX_CP_REG_TEST_0_REG__MASK 0x00000fff 1556 #define A2XX_CP_REG_TEST_0_REG__SHIFT 0 1557 static inline uint32_t A2XX_CP_REG_TEST_0_REG(uint32_t val) 1558 { 1559 return ((val) << A2XX_CP_REG_TEST_0_REG__SHIFT) & A2XX_CP_REG_TEST_0_REG__MASK; 1560 } 1561 #define A2XX_CP_REG_TEST_0_BIT__MASK 0x01f00000 1562 #define A2XX_CP_REG_TEST_0_BIT__SHIFT 20 1563 static inline uint32_t A2XX_CP_REG_TEST_0_BIT(uint32_t val) 1564 { 1565 return ((val) << A2XX_CP_REG_TEST_0_BIT__SHIFT) & A2XX_CP_REG_TEST_0_BIT__MASK; 1566 } 1567 #define A2XX_CP_REG_TEST_0_UNK25 0x02000000 1568 1569 1570 #endif /* ADRENO_PM4_XML */ 1571
Indexes created Sat Aug 01 00:24:56 UTC 2026