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    Searched defs:SC (Results 1 - 25 of 58) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
CloneModule.cpp 22 const Comdat *SC = Src->getComdat();
23 if (!SC)
25 Comdat *DC = Dst->getParent()->getOrInsertComdat(SC->getName());
26 DC->setSelectionKind(SC->getSelectionKind());
  /src/external/apache2/llvm/dist/llvm/lib/MCA/Stages/
InOrderIssueStage.cpp 102 const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID);
108 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID);
131 assert(STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID) < 0);
133 -STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID));
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZMachineScheduler.cpp 255 const MCSchedClassDesc *SC = HazardRec->getSchedClass(SU);
256 bool AffectsGrouping = (SC->isValid() && (SC->BeginGroup || SC->EndGroup));
SystemZHazardRecognizer.cpp 47 const MCSchedClassDesc *SC = getSchedClass(SU);
48 if (!SC->isValid())
51 assert((SC->NumMicroOps != 2 || (SC->BeginGroup && !SC->EndGroup)) &&
53 assert((SC->NumMicroOps < 3 || (SC->BeginGroup && SC->EndGroup)) &&
55 assert((SC->NumMicroOps < 3 || (SC->NumMicroOps % 3 == 0)) &
    [all...]
  /src/external/apache2/llvm/dist/clang/lib/ARCMigrate/
TransProtectedScope.cpp 42 SwitchCase *SC;
50 CaseInfo() : SC(nullptr), State(St_Unchecked) {}
52 : SC(S), Range(Range), State(St_Unchecked) {}
176 Pass.TA.insertAfterToken(info.SC->getColonLoc(), " {");
  /src/external/apache2/llvm/dist/llvm/tools/llvm-pdbutil/
InputFile.h 124 codeview::StringsAndChecksumsRef SC;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MachineTraceMetrics.cpp 122 const MCSchedClassDesc *SC = SchedModel.resolveSchedClass(&MI);
123 if (!SC->isValid())
127 PI = SchedModel.getWriteProcResBegin(SC),
128 PE = SchedModel.getWriteProcResEnd(SC); PI != PE; ++PI) {
1238 for (const MCSchedClassDesc *SC : Instrs) {
1239 if (!SC->isValid())
1242 PI = TE.MTM.SchedModel.getWriteProcResBegin(SC),
1243 PE = TE.MTM.SchedModel.getWriteProcResEnd(SC);
  /src/external/apache2/llvm/dist/llvm/lib/Linker/
LinkModules.cpp 380 if (const Comdat *SC = GV.getComdat()) {
383 std::tie(SK, LinkFromSrc) = ComdatsChosen[SC];
406 const Comdat *SC = GV.getComdat();
407 if (!SC)
409 for (GlobalValue *GV2 : LazyComdatMembers[SC]) {
503 if (const Comdat *SC = GV.getComdat())
504 LazyComdatMembers[SC].push_back(&GV);
508 if (const Comdat *SC = SF.getComdat())
509 LazyComdatMembers[SC].push_back(&SF);
513 if (const Comdat *SC = GA.getComdat()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/
RegisterFile.cpp 480 const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID);
496 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID);
511 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID);
560 const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID);
564 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID);
571 assert(STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID) < 0);
573 -STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID));
  /src/external/apache2/llvm/dist/llvm/tools/obj2yaml/
coff2yaml.cpp 101 codeview::StringsAndChecksumsRef &SC) {
107 if (SC.hasStrings() && SC.hasChecksums())
133 SC.initialize(Subsections);
139 codeview::StringsAndChecksumsRef SC;
140 initializeFileAndStringTable(Obj, SC);
185 NewYAMLSection.DebugS = CodeViewYAML::fromDebugS(sectionData, SC);
  /src/external/gpl3/binutils/dist/opcodes/
msp430-decode.c 88 #define SC(c) OP (1, MSP430_Operand_Immediate, 0, c)
205 SC (0);
224 SC (1);
236 SC (4);
239 SC (2);
256 SC (x);
260 SC (8);
263 SC (-1);
552 ID (MSO_mov); SC ((srcr << 16) + IMMU(2)); DR (dstr);
576 ID (MSO_cmp); SC ((srcr << 16) + IMMU(2)); DR (dstr)
    [all...]
rl78-decode.c 126 #define SC(c) OP (1, RL78_Operand_Immediate, 0, c)
265 ID(add); W(); DR(AX); SC(IMMU(2)); Fzac;
327 ID(add); DM(None, SADDR); SC(IMMU(1)); Fzac;
359 ID(add); DR(A); SC(IMMU(1)); Fzac;
419 ID(add); W(); DR(SP); SC(IMMU(1)); Fzac;
511 ID(mov); DM(B, IMMU(2)); SC(IMMU(1));
526 ID(addc); DM(None, SADDR); SC(IMMU(1)); Fzac;
558 ID(addc); DR(A); SC(IMMU(1)); Fzac;
618 ID(sub); W(); DR(SP); SC(IMMU(1)); Fzac;
671 ID(sub); W(); DR(AX); SC(IMMU(2)); Fzac
    [all...]
rx-decode.c 131 #define SC(i) OP (1, RX_Operand_Immediate, 0, i)
3856 ID(mov); sBWL (sz); DIs(dst, d*16+sppp, sz); SC(IMM(1)); F_____;
3901 ID(rtsd); SC(IMM(1) * 4); S2R(rega); DR(regb);
4430 ID(add); SC(immm); DR(rdst); F_OSZC;
4466 DR(rdst); SC(immm); F_____;
4493 ID(and); SC(immm); DR(rdst); F__SZ_;
4520 ID(or); SC(immm); DR(rdst); F__SZ_;
4547 ID(mov); DR(rdst); SC(immm); F_____;
4564 ID(rtsd); SC(IMM(1) * 4);
4767 ID(add); SC(IMMex(im)); S2R(rsrc); DR(rdst); F_OSZC
    [all...]
  /src/external/gpl3/binutils.old/dist/opcodes/
msp430-decode.c 88 #define SC(c) OP (1, MSP430_Operand_Immediate, 0, c)
205 SC (0);
224 SC (1);
236 SC (4);
239 SC (2);
256 SC (x);
260 SC (8);
263 SC (-1);
552 ID (MSO_mov); SC ((srcr << 16) + IMMU(2)); DR (dstr);
576 ID (MSO_cmp); SC ((srcr << 16) + IMMU(2)); DR (dstr)
    [all...]
rl78-decode.c 126 #define SC(c) OP (1, RL78_Operand_Immediate, 0, c)
265 ID(add); W(); DR(AX); SC(IMMU(2)); Fzac;
327 ID(add); DM(None, SADDR); SC(IMMU(1)); Fzac;
359 ID(add); DR(A); SC(IMMU(1)); Fzac;
419 ID(add); W(); DR(SP); SC(IMMU(1)); Fzac;
511 ID(mov); DM(B, IMMU(2)); SC(IMMU(1));
526 ID(addc); DM(None, SADDR); SC(IMMU(1)); Fzac;
558 ID(addc); DR(A); SC(IMMU(1)); Fzac;
618 ID(sub); W(); DR(SP); SC(IMMU(1)); Fzac;
671 ID(sub); W(); DR(AX); SC(IMMU(2)); Fzac
    [all...]
rx-decode.c 131 #define SC(i) OP (1, RX_Operand_Immediate, 0, i)
3856 ID(mov); sBWL (sz); DIs(dst, d*16+sppp, sz); SC(IMM(1)); F_____;
3901 ID(rtsd); SC(IMM(1) * 4); S2R(rega); DR(regb);
4430 ID(add); SC(immm); DR(rdst); F_OSZC;
4466 DR(rdst); SC(immm); F_____;
4493 ID(and); SC(immm); DR(rdst); F__SZ_;
4520 ID(or); SC(immm); DR(rdst); F__SZ_;
4547 ID(mov); DR(rdst); SC(immm); F_____;
4564 ID(rtsd); SC(IMM(1) * 4);
4767 ID(add); SC(IMMex(im)); S2R(rsrc); DR(rdst); F_OSZC
    [all...]
  /src/external/gpl3/gdb.old/dist/opcodes/
msp430-decode.c 88 #define SC(c) OP (1, MSP430_Operand_Immediate, 0, c)
205 SC (0);
224 SC (1);
236 SC (4);
239 SC (2);
256 SC (x);
260 SC (8);
263 SC (-1);
552 ID (MSO_mov); SC ((srcr << 16) + IMMU(2)); DR (dstr);
576 ID (MSO_cmp); SC ((srcr << 16) + IMMU(2)); DR (dstr)
    [all...]
rl78-decode.c 126 #define SC(c) OP (1, RL78_Operand_Immediate, 0, c)
265 ID(add); W(); DR(AX); SC(IMMU(2)); Fzac;
327 ID(add); DM(None, SADDR); SC(IMMU(1)); Fzac;
359 ID(add); DR(A); SC(IMMU(1)); Fzac;
419 ID(add); W(); DR(SP); SC(IMMU(1)); Fzac;
511 ID(mov); DM(B, IMMU(2)); SC(IMMU(1));
526 ID(addc); DM(None, SADDR); SC(IMMU(1)); Fzac;
558 ID(addc); DR(A); SC(IMMU(1)); Fzac;
618 ID(sub); W(); DR(SP); SC(IMMU(1)); Fzac;
671 ID(sub); W(); DR(AX); SC(IMMU(2)); Fzac
    [all...]
rx-decode.c 131 #define SC(i) OP (1, RX_Operand_Immediate, 0, i)
3856 ID(mov); sBWL (sz); DIs(dst, d*16+sppp, sz); SC(IMM(1)); F_____;
3901 ID(rtsd); SC(IMM(1) * 4); S2R(rega); DR(regb);
4430 ID(add); SC(immm); DR(rdst); F_OSZC;
4466 DR(rdst); SC(immm); F_____;
4493 ID(and); SC(immm); DR(rdst); F__SZ_;
4520 ID(or); SC(immm); DR(rdst); F__SZ_;
4547 ID(mov); DR(rdst); SC(immm); F_____;
4564 ID(rtsd); SC(IMM(1) * 4);
4767 ID(add); SC(IMMex(im)); S2R(rsrc); DR(rdst); F_OSZC
    [all...]
  /src/external/gpl3/gdb/dist/opcodes/
msp430-decode.c 88 #define SC(c) OP (1, MSP430_Operand_Immediate, 0, c)
205 SC (0);
224 SC (1);
236 SC (4);
239 SC (2);
256 SC (x);
260 SC (8);
263 SC (-1);
552 ID (MSO_mov); SC ((srcr << 16) + IMMU(2)); DR (dstr);
576 ID (MSO_cmp); SC ((srcr << 16) + IMMU(2)); DR (dstr)
    [all...]
rl78-decode.c 126 #define SC(c) OP (1, RL78_Operand_Immediate, 0, c)
265 ID(add); W(); DR(AX); SC(IMMU(2)); Fzac;
327 ID(add); DM(None, SADDR); SC(IMMU(1)); Fzac;
359 ID(add); DR(A); SC(IMMU(1)); Fzac;
419 ID(add); W(); DR(SP); SC(IMMU(1)); Fzac;
511 ID(mov); DM(B, IMMU(2)); SC(IMMU(1));
526 ID(addc); DM(None, SADDR); SC(IMMU(1)); Fzac;
558 ID(addc); DR(A); SC(IMMU(1)); Fzac;
618 ID(sub); W(); DR(SP); SC(IMMU(1)); Fzac;
671 ID(sub); W(); DR(AX); SC(IMMU(2)); Fzac
    [all...]
  /src/sys/dev/mscp/
mscp_subr.c 794 #define SC(m) sizeof (m) / sizeof (m[0]), m
795 {"success", SC(succ_msgs)},
796 {"invalid command", SC(icmd_msgs)},
798 {"unit offline", SC(offl_msgs)},
800 {"media format error", SC(media_fmt_msgs)},
801 {"write protected", SC(wrprot_msgs)},
803 {"data error", SC(data_msgs)},
804 {"host buffer access error", SC(host_buffer_msgs)},
805 {"controller error", SC(cntlr_msgs)},
806 {"drive error", SC(drive_msgs)}
818 int c, sc; local
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
ScalarEvolution.cpp 408 if (const SCEVConstant *SC = dyn_cast<SCEVConstant>(this))
409 return SC->getValue()->isZero();
414 if (const SCEVConstant *SC = dyn_cast<SCEVConstant>(this))
415 return SC->getValue()->isOne();
420 if (const SCEVConstant *SC = dyn_cast<SCEVConstant>(this))
421 return SC->getValue()->isMinusOne();
430 const SCEVConstant *SC = dyn_cast<SCEVConstant>(Mul->getOperand(0));
431 if (!SC) return false;
434 return SC->getAPInt().isNegative();
1192 if (const SCEVConstant *SC = dyn_cast<SCEVConstant>(Op)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsExpandPseudo.cpp 16 // spills between ll and sc. These stores cause some MIPS implementations to
82 unsigned LL, SC;
92 SC = STI->hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM;
98 SC = STI->hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
99 : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
155 // sc dest, dest, 0(ptr)
163 BuildMI(loop2MBB, DL, TII->get(SC), Scratch)
213 unsigned LL, SC, ZERO, BNE, BEQ, MOVE;
218 SC = STI->hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM;
225 SC = STI->hasMips32r6(
    [all...]
  /src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Checkers/RetainCountChecker/
RetainCountDiagnostics.cpp 360 const StackFrameContext *SC = Pred->getStackFrame();
361 if (SC->inTopFrame())
363 const StackFrameContext *PC = SC->getParent()->getStackFrame();

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