1 /* $NetBSD: btcd.h,v 1.3 2021/12/18 23:45:42 riastradh Exp $ */ 2 3 /* 4 * Copyright 2010 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Alex Deucher 25 */ 26 #ifndef _BTCD_H_ 27 #define _BTCD_H_ 28 29 /* pm registers */ 30 31 #define GENERAL_PWRMGT 0x63c 32 # define GLOBAL_PWRMGT_EN (1 << 0) 33 # define STATIC_PM_EN (1 << 1) 34 # define THERMAL_PROTECTION_DIS (1 << 2) 35 # define THERMAL_PROTECTION_TYPE (1 << 3) 36 # define ENABLE_GEN2PCIE (1 << 4) 37 # define ENABLE_GEN2XSP (1 << 5) 38 # define SW_SMIO_INDEX(x) ((x) << 6) 39 # define SW_SMIO_INDEX_MASK (3 << 6) 40 # define SW_SMIO_INDEX_SHIFT 6 41 # define LOW_VOLT_D2_ACPI (1 << 8) 42 # define LOW_VOLT_D3_ACPI (1 << 9) 43 # define VOLT_PWRMGT_EN (1 << 10) 44 # define BACKBIAS_PAD_EN (1 << 18) 45 # define BACKBIAS_VALUE (1 << 19) 46 # define DYN_SPREAD_SPECTRUM_EN (1 << 23) 47 # define AC_DC_SW (1 << 24) 48 49 #define TARGET_AND_CURRENT_PROFILE_INDEX 0x66c 50 # define CURRENT_PROFILE_INDEX_MASK (0xf << 4) 51 # define CURRENT_PROFILE_INDEX_SHIFT 4 52 53 #define CG_BIF_REQ_AND_RSP 0x7f4 54 #define CG_CLIENT_REQ(x) ((x) << 0) 55 #define CG_CLIENT_REQ_MASK (0xff << 0) 56 #define CG_CLIENT_REQ_SHIFT 0 57 #define CG_CLIENT_RESP(x) ((x) << 8) 58 #define CG_CLIENT_RESP_MASK (0xff << 8) 59 #define CG_CLIENT_RESP_SHIFT 8 60 #define CLIENT_CG_REQ(x) ((x) << 16) 61 #define CLIENT_CG_REQ_MASK (0xff << 16) 62 #define CLIENT_CG_REQ_SHIFT 16 63 #define CLIENT_CG_RESP(x) ((x) << 24) 64 #define CLIENT_CG_RESP_MASK (0xff << 24) 65 #define CLIENT_CG_RESP_SHIFT 24 66 67 #define SCLK_PSKIP_CNTL 0x8c0 68 #define PSKIP_ON_ALLOW_STOP_HI(x) ((x) << 16) 69 #define PSKIP_ON_ALLOW_STOP_HI_MASK (0xff << 16) 70 #define PSKIP_ON_ALLOW_STOP_HI_SHIFT 16 71 72 #define CG_ULV_CONTROL 0x8c8 73 #define CG_ULV_PARAMETER 0x8cc 74 75 #define MC_ARB_DRAM_TIMING 0x2774 76 #define MC_ARB_DRAM_TIMING2 0x2778 77 78 #define MC_ARB_RFSH_RATE 0x27b0 79 #define POWERMODE0(x) ((x) << 0) 80 #define POWERMODE0_MASK (0xff << 0) 81 #define POWERMODE0_SHIFT 0 82 #define POWERMODE1(x) ((x) << 8) 83 #define POWERMODE1_MASK (0xff << 8) 84 #define POWERMODE1_SHIFT 8 85 #define POWERMODE2(x) ((x) << 16) 86 #define POWERMODE2_MASK (0xff << 16) 87 #define POWERMODE2_SHIFT 16 88 #define POWERMODE3(x) ((x) << 24) 89 #define POWERMODE3_MASK (0xff << 24) 90 #define POWERMODE3_SHIFT 24 91 92 #define MC_ARB_BURST_TIME 0x2808 93 #define STATE0(x) ((x) << 0) 94 #define STATE0_MASK (0x1f << 0) 95 #define STATE0_SHIFT 0 96 #define STATE1(x) ((x) << 5) 97 #define STATE1_MASK (0x1f << 5) 98 #define STATE1_SHIFT 5 99 #define STATE2(x) ((x) << 10) 100 #define STATE2_MASK (0x1f << 10) 101 #define STATE2_SHIFT 10 102 #define STATE3(x) ((x) << 15) 103 #define STATE3_MASK (0x1f << 15) 104 #define STATE3_SHIFT 15 105 106 #define MC_SEQ_RAS_TIMING 0x28a0 107 #define MC_SEQ_CAS_TIMING 0x28a4 108 #define MC_SEQ_MISC_TIMING 0x28a8 109 #define MC_SEQ_MISC_TIMING2 0x28ac 110 111 #define MC_SEQ_RD_CTL_D0 0x28b4 112 #define MC_SEQ_RD_CTL_D1 0x28b8 113 #define MC_SEQ_WR_CTL_D0 0x28bc 114 #define MC_SEQ_WR_CTL_D1 0x28c0 115 116 #define MC_PMG_AUTO_CFG 0x28d4 117 118 #define MC_SEQ_STATUS_M 0x29f4 119 # define PMG_PWRSTATE (1 << 16) 120 121 #define MC_SEQ_MISC0 0x2a00 122 #define MC_SEQ_MISC0_GDDR5_SHIFT 28 123 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 124 #define MC_SEQ_MISC0_GDDR5_VALUE 5 125 #define MC_SEQ_MISC1 0x2a04 126 #define MC_SEQ_RESERVE_M 0x2a08 127 #define MC_PMG_CMD_EMRS 0x2a0c 128 129 #define MC_SEQ_MISC3 0x2a2c 130 131 #define MC_SEQ_MISC5 0x2a54 132 #define MC_SEQ_MISC6 0x2a58 133 134 #define MC_SEQ_MISC7 0x2a64 135 136 #define MC_SEQ_CG 0x2a68 137 #define CG_SEQ_REQ(x) ((x) << 0) 138 #define CG_SEQ_REQ_MASK (0xff << 0) 139 #define CG_SEQ_REQ_SHIFT 0 140 #define CG_SEQ_RESP(x) ((x) << 8) 141 #define CG_SEQ_RESP_MASK (0xff << 8) 142 #define CG_SEQ_RESP_SHIFT 8 143 #define SEQ_CG_REQ(x) ((x) << 16) 144 #define SEQ_CG_REQ_MASK (0xff << 16) 145 #define SEQ_CG_REQ_SHIFT 16 146 #define SEQ_CG_RESP(x) ((x) << 24) 147 #define SEQ_CG_RESP_MASK (0xff << 24) 148 #define SEQ_CG_RESP_SHIFT 24 149 #define MC_SEQ_RAS_TIMING_LP 0x2a6c 150 #define MC_SEQ_CAS_TIMING_LP 0x2a70 151 #define MC_SEQ_MISC_TIMING_LP 0x2a74 152 #define MC_SEQ_MISC_TIMING2_LP 0x2a78 153 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c 154 #define MC_SEQ_WR_CTL_D1_LP 0x2a80 155 #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84 156 #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88 157 158 #define MC_PMG_CMD_MRS 0x2aac 159 160 #define MC_SEQ_RD_CTL_D0_LP 0x2b1c 161 #define MC_SEQ_RD_CTL_D1_LP 0x2b20 162 163 #define MC_PMG_CMD_MRS1 0x2b44 164 #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48 165 166 #define LB_SYNC_RESET_SEL 0x6b28 167 #define LB_SYNC_RESET_SEL_MASK (3 << 0) 168 #define LB_SYNC_RESET_SEL_SHIFT 0 169 170 /* PCIE link stuff */ 171 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 172 # define LC_GEN2_EN_STRAP (1 << 0) 173 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 174 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 175 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 176 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 177 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 178 # define LC_CURRENT_DATA_RATE (1 << 11) 179 # define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12) 180 # define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12) 181 # define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12 182 # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 183 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 184 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 185 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 186 187 #endif 188
Indexes created Mon Sep 29 21:09:56 GMT 2025