1 /* $NetBSD: scireg.h,v 1.10 2013/05/14 13:53:47 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (C) 1999 SAITOH Masanobu. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _SH3_SCIREG_H_ 30 #define _SH3_SCIREG_H_ 31 32 /* 33 * Serial Communication Interface (SCI) 34 */ 35 36 #if !defined(SH4) 37 38 /* SH3 definitions */ 39 40 #define SHREG_SCSMR (*(volatile unsigned char *) 0xFFFFFE80) 41 #define SHREG_SCBRR (*(volatile unsigned char *) 0xFFFFFE82) 42 #define SHREG_SCSCR (*(volatile unsigned char *) 0xFFFFFE84) 43 #define SHREG_SCTDR (*(volatile unsigned char *) 0xFFFFFE86) 44 #define SHREG_SCSSR (*(volatile unsigned char *) 0xFFFFFE88) 45 #define SHREG_SCRDR (*(volatile unsigned char *) 0xFFFFFE8A) 46 #define SHREG_SCSCMR (*(volatile unsigned char *) 0xFFFFFE8C) 47 #define SHREG_SCSPDR (*(volatile unsigned char *) 0xf4000136) 48 49 #else 50 51 /* SH4 definitions */ 52 53 #define SHREG_SCSMR (*(volatile unsigned char *) 0xffe00000) 54 #define SHREG_SCBRR (*(volatile unsigned char *) 0xffe00004) 55 #define SHREG_SCSCR (*(volatile unsigned char *) 0xffe00008) 56 #define SHREG_SCTDR (*(volatile unsigned char *) 0xffe0000c) 57 #define SHREG_SCSSR (*(volatile unsigned char *) 0xffe00010) 58 #define SHREG_SCRDR (*(volatile unsigned char *) 0xffe00014) 59 #define SHREG_SCSCMR (*(volatile unsigned char *) 0xffe00018) 60 #define SHREG_SCSPTR (*(volatile unsigned char *) 0xffe0001c) 61 62 #endif 63 64 #define SCSMR_CA 0x80 65 #define SCSMR_CHR 0x40 66 #define SCSMR_PE 0x20 67 #define SCSMR_OE 0x10 68 #define SCSMR_STOP 0x08 69 #define SCSMR_MP 0x04 70 #define SCSMR_CKS1 0x02 71 #define SCSMR_CKS0 0x01 72 73 #define SCSCR_TIE 0x80 /* Transmit Interrupt Enable */ 74 #define SCSCR_RIE 0x40 /* Receive Interrupt Enable */ 75 #define SCSCR_TE 0x20 /* Transmit Enable */ 76 #define SCSCR_RE 0x10 /* Receive Enable */ 77 #define SCSCR_MPIE 0x08 /* Multi Processor Interrupt Enable */ 78 #define SCSCR_TEIE 0x04 /* Transmit End Interrupt Enable */ 79 #define SCSCR_CKE1 0x02 /* ClocK Enable 1 */ 80 #define SCSCR_CKE0 0x01 /* ClocK Enable 0 */ 81 82 #define SCSSR_TDRE 0x80 83 #define SCSSR_RDRF 0x40 84 #define SCSSR_ORER 0x20 85 #define SCSSR_FER 0x10 86 #define SCSSR_PER 0x08 87 #define SCSSR_TEND 0x04 88 #define SCSSR_MPB 0x02 89 #define SCSSR_MPBT 0x01 90 91 #define SCSPTR_SPB1IO 0x08 92 #define SCSPTR_SPB1DT 0x04 93 #define SCSPTR_SPB0IO 0x02 94 #define SCSPTR_SPB0DT 0x01 95 96 #if defined(SH3) 97 #define SCSPDR_SCP0DT 0x01 98 #endif 99 100 #endif /* !_SH3_SCIREG_ */ 101
Indexes created Sun Sep 21 14:09:52 GMT 2025