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      1 /*	$NetBSD: bestcommreg.h,v 1.1 2026/06/27 13:28:34 rkujawa Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2026 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Radoslaw Kujawa.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #ifndef _POWERPC_MPC5200_BESTCOMMREG_H_
     33 #define _POWERPC_MPC5200_BESTCOMMREG_H_
     34 
     35 /*
     36  * BestComm SDMA controller registers (MBAR+0x1200 block).
     37  */
     38 
     39 #define	SDMA_TASKBAR	0x00	/* task table base (physical SRAM addr)	*/
     40 #define	SDMA_CUR_PTR	0x04	/* current descriptor pointer		*/
     41 #define	SDMA_END_PTR	0x08	/* end descriptor pointer		*/
     42 #define	SDMA_VAR_PTR	0x0c	/* variable table pointer		*/
     43 #define	SDMA_INT_VECT1	0x10	/* interrupt vector 1 (8-bit)		*/
     44 #define	SDMA_INT_VECT2	0x11	/* interrupt vector 2 (8-bit)		*/
     45 #define	SDMA_PTD_CNTRL	0x12	/* processor task dispatch control (16-bit) */
     46 #define	SDMA_INT_PEND	0x14	/* interrupt pending (write 1 to clear)	*/
     47 #define	SDMA_INT_MASK	0x18	/* interrupt mask (1 = masked)		*/
     48 #define	SDMA_TCR	0x1c	/* task control regs: 16 x 16-bit	*/
     49 #define	SDMA_IPR	0x3c	/* initiator priority regs: 32 x 8-bit	*/
     50 #define	SDMA_CREQ_SEL	0x5c	/* current request select		*/
     51 #define	SDMA_TASK_SIZE0	0x60	/* task size 0				*/
     52 #define	SDMA_TASK_SIZE1	0x64	/* task size 1				*/
     53 #define	SDMA_MDE_DEBUG	0x68	/* MDE debug				*/
     54 #define	SDMA_ADS_DEBUG	0x6c	/* ADS debug				*/
     55 #define	SDMA_VALUE1	0x70	/* debug value 1			*/
     56 #define	SDMA_VALUE2	0x74	/* debug value 2			*/
     57 #define	SDMA_DBG_CONTROL 0x78	/* debug control			*/
     58 #define	SDMA_DBG_STATUS	0x7c	/* debug status				*/
     59 #define	SDMA_PTD_DEBUG	0x80	/* PTD debug				*/
     60 
     61 #define	SDMA_REG_SIZE	0x100	/* register window if OF omits a size	*/
     62 
     63 /*
     64  * Per-task control register (TCR).
     65  */
     66 #define	SDMA_TCR_TASK(n)	(SDMA_TCR + (n) * 2)
     67 #define	SDMA_TCR_ENABLE		0x8000	/* enable/start this task (bit 15)	*/
     68 #define	SDMA_TCR_INIT_SHIFT	8	/* initiator number field (bits 8-12)	*/
     69 #define	SDMA_TCR_INIT_MASK	0x1f00
     70 #define	SDMA_TCR_HOLD		0x0020	/* hold initiator (bit 5)		*/
     71 #define	SDMA_TCR_AUTOSTART	0x0080	/* restart after completion (bit 7)	*/
     72 #define	SDMA_TCR_AUTOTASK_MASK	0x000f	/* task to auto-start (bits 0-3)		*/
     73 
     74 #define	SDMA_NTASKS		16	/* number of SDMA tasks		*/
     75 
     76 /*
     77  * Per-task transfer-size register
     78  */
     79 #define	SDMA_SIZE_BYTE(task)	(SDMA_TASK_SIZE0 + (task) / 2)
     80 #define	SDMA_SIZE_CODE(sz)	((sz) & 0x3)
     81 #define	SDMA_SIZE_FIELD(src, dst) \
     82 	((SDMA_SIZE_CODE(src) << 2) | SDMA_SIZE_CODE(dst))
     83 
     84 /*
     85  * Data Routing Descriptor (DRD)
     86  */
     87 #define	SDMA_DRD_INIT_SHIFT	21
     88 #define	SDMA_DRD_INIT_MASK	(0x1fu << SDMA_DRD_INIT_SHIFT)	/* 0x03e00000 */
     89 #define	SDMA_DRD_EXT		0x40000000
     90 #define	SDMA_INITIATOR_ALWAYS	0
     91 
     92 /* Per-initiator priority registers: byte SDMA_IPR + initiator */
     93 #define	SDMA_IPR_INIT(init)	(SDMA_IPR + (init))
     94 
     95 /* PtdCntrl (SDMA_PTD_CNTRL) bits. */
     96 #define	SDMA_PTD_CNTRL_TI	0x8000	/* task initiator disable	*/
     97 #define	SDMA_PTD_CNTRL_TEA	0x4000	/* bus-error (TEA) disable	*/
     98 #define	SDMA_PTD_CNTRL_HE	0x2000	/* halt on error		*/
     99 #define	SDMA_PTD_CNTRL_PE	0x0001	/* parity enable		*/
    100 
    101 /*
    102  * Interrupt pending / mask register layout.
    103  */
    104 #define	SDMA_INT_TASK_MASK	0x0000ffff	/* the 16 task events	*/
    105 #define	SDMA_INT_TASK(n)	(1u << (n))
    106 #define	SDMA_INT_TEA		__BIT(28)	/* XLB bus error	*/
    107 #define	SDMA_INT_TEA_TASK_MASK	0x0f000000	/* faulting task (bits 24-27) */
    108 #define	SDMA_INT_TEA_TASK_SHIFT	24
    109 #define	SDMA_INT_DBG		__BIT(31)	/* debug event		*/
    110 #define	SDMA_INT_IMPL		0x9000ffff	/* implemented bits	*/
    111 
    112 #endif /* _POWERPC_MPC5200_BESTCOMMREG_H_ */
    113