1 /* -*-C++-*- $NetBSD: sh.h,v 1.6 2021/10/06 20:36:58 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _HPCBOOT_SH_DEV_SH_H_ 33 #define _HPCBOOT_SH_DEV_SH_H_ 34 35 /* 36 * SH3, SH4 embedded devices. 37 */ 38 39 /* 40 * INTC 41 */ 42 /* SH7709/7709A */ 43 /* R/W 16bit */ 44 #define SH3_ICR0 0xfffffee0 45 #define SH3_ICR1 0xa4000010 46 #define SH3_ICR2 0xa4000012 47 #define SH3_PINTER 0xa4000014 48 #define SH3_IPRA 0xfffffee2 49 #define SH3_IPRB 0xfffffee4 50 #define SH3_IPRC 0xa4000016 51 #define SH3_IPRD 0xa4000018 52 #define SH3_IPRE 0xa400001a 53 /* R/W 8bit */ 54 #define SH3_IRR0 0xa4000004 55 /* R 8bit */ 56 #define SH3_IRR1 0xa4000006 57 #define SH3_IRR2 0xa4000008 58 59 #define SH3_ICR0_NMIL 0x8000 60 #define SH3_ICR0_NMIE 0x0100 61 62 #define SH3_ICR1_MAI 0x8000 63 #define SH3_ICR1_IRQLVL 0x4000 64 #define SH3_ICR1_BLMSK 0x2000 65 #define SH3_ICR1_IRLSEN 0x1000 66 #define SH3_ICR1_IRQ51S 0x0800 67 #define SH3_ICR1_IRQ50S 0x0400 68 #define SH3_ICR1_IRQ41S 0x0200 69 #define SH3_ICR1_IRQ40S 0x0100 70 #define SH3_ICR1_IRQ31S 0x0080 71 #define SH3_ICR1_IRQ30S 0x0040 72 #define SH3_ICR1_IRQ21S 0x0020 73 #define SH3_ICR1_IRQ20S 0x0010 74 #define SH3_ICR1_IRQ11S 0x0008 75 #define SH3_ICR1_IRQ10S 0x0004 76 #define SH3_ICR1_IRQ01S 0x0002 77 #define SH3_ICR1_IRQ00S 0x0001 78 79 #define SH3_SENSE_SELECT_MASK 0x3 80 #define SH3_SENSE_SELECT_FALLING_EDGE 0x0 81 #define SH3_SENSE_SELECT_RAISING_EDGE 0x1 82 #define SH3_SENSE_SELECT_LOW_LEVEL 0x2 83 #define SH3_SENSE_SELECT_RESERVED 0x3 84 85 #define SH3_ICR2_PINT15S 0x8000 86 #define SH3_ICR2_PINT14S 0x4000 87 #define SH3_ICR2_PINT13S 0x2000 88 #define SH3_ICR2_PINT12S 0x1000 89 #define SH3_ICR2_PINT11S 0x0800 90 #define SH3_ICR2_PINT10S 0x0400 91 #define SH3_ICR2_PINT9S 0x0200 92 #define SH3_ICR2_PINT8S 0x0100 93 #define SH3_ICR2_PINT7S 0x0080 94 #define SH3_ICR2_PINT6S 0x0040 95 #define SH3_ICR2_PINT5S 0x0020 96 #define SH3_ICR2_PINT4S 0x0010 97 #define SH3_ICR2_PINT3S 0x0008 98 #define SH3_ICR2_PINT2S 0x0004 99 #define SH3_ICR2_PINT1S 0x0002 100 #define SH3_ICR2_PINT0S 0x0001 101 102 #define SH_IPR_MASK 0xf 103 104 /* SH7750 */ 105 #define SH4_ICR 0xffd00000 106 #define SH4_ICR_NMIL 0x8000 107 #define SH4_ICR_MAI 0x4000 108 #define SH4_ICR_NMIB 0x0200 109 #define SH4_ICR_NMIE 0x0100 110 #define SH4_ICR_IRLM 0x0080 111 #define SH4_IPRA 0xffd00004 112 #define SH4_IPRB 0xffd00008 113 #define SH4_IPRC 0xffd0000c 114 /* SH7750S */ 115 #define SH4_IPRD 0xffd00010 116 117 /* 118 * Bus State Controller 119 */ 120 #define SH3_BCR1 0xffffff60 121 #define SH3_BCR2 0xffffff62 122 #define SH3_WCR1 0xffffff64 123 #define SH3_WCR2 0xffffff66 124 #define SH3_MCR 0xffffff68 125 #define SH3_DCR 0xffffff6a 126 #define SH3_PCR 0xffffff6c 127 #define SH3_RTCSR 0xffffff6e 128 #define SH3_RTCNT 0xffffff70 129 #define SH3_RTCOR 0xffffff72 130 #define SH3_RFCR 0xffffff74 131 #define SH3_BCR3 0xffffff7e 132 133 /* 134 * Pin Function Controller 135 */ 136 #define SH3_PACR 0xa4000100 137 #define SH3_PBCR 0xa4000102 138 #define SH3_PCCR 0xa4000104 139 #define SH3_PDCR 0xa4000106 140 #define SH3_PECR 0xa4000108 141 #define SH3_PFCR 0xa400010a 142 #define SH3_PGCR 0xa400010c 143 #define SH3_PHCR 0xa400010e 144 #define SH3_PJCR 0xa4000110 145 #define SH3_PKCR 0xa4000112 146 #define SH3_PLCR 0xa4000114 147 #define SH3_SCPCR 0xa4000116 148 149 /* 150 * I/O port 151 */ 152 #define SH3_PADR 0xa4000120 153 #define SH3_PBDR 0xa4000122 154 #define SH3_PCDR 0xa4000124 155 #define SH3_PDDR 0xa4000126 156 #define SH3_PEDR 0xa4000128 157 #define SH3_PFDR 0xa400012a 158 #define SH3_PGDR 0xa400012c 159 #define SH3_PHDR 0xa400012e 160 #define SH3_PJDR 0xa4000130 161 #define SH3_PKDR 0xa4000132 162 #define SH3_PLDR 0xa4000134 163 #define SH3_SCPDR 0xa4000136 164 165 /* 166 * TMU 167 */ 168 #define SH3_TOCR 0xfffffe90 169 #define SH3_TOCR_TCOE 0x01 170 #define SH3_TSTR 0xfffffe92 171 #define SH3_TSTR_STR2 0x04 172 #define SH3_TSTR_STR1 0x02 173 #define SH3_TSTR_STR0 0x01 174 #define SH3_TCOR0 0xfffffe94 175 #define SH3_TCNT0 0xfffffe98 176 #define SH3_TCR0 0xfffffe9c 177 #define SH3_TCOR1 0xfffffea0 178 #define SH3_TCNT1 0xfffffea4 179 #define SH3_TCR1 0xfffffea8 180 #define SH3_TCOR2 0xfffffeac 181 #define SH3_TCNT2 0xfffffeb0 182 #define SH3_TCR2 0xfffffeb4 183 #define SH3_TCPR2 0xfffffeb8 184 #define SH3_TCR_ICPF 0x0200 185 #define SH3_TCR_UNF 0x0100 186 #define SH3_TCR_ICPE1 0x0080 187 #define SH3_TCR_ICPE0 0x0040 188 #define SH3_TCR_UNIE 0x0020 189 #define SH3_TCR_CKEG1 0x0010 190 #define SH3_TCR_CKEG0 0x0008 191 #define SH3_TCR_TPSC2 0x0004 192 #define SH3_TCR_TPSC1 0x0002 193 #define SH3_TCR_TPSC0 0x0001 194 195 #define SH3_TCR_TPSC_P4 0x0000 196 #define SH3_TCR_TPSC_P16 0x0001 197 #define SH3_TCR_TPSC_P64 0x0002 198 #define SH3_TCR_TPSC_P256 0x0003 199 200 /* 201 * SCI 202 */ 203 #define SH4_SCSMR 0xffe00000 204 #define SH4_SCBRR 0xffe00004 205 #define SH4_SCSCR 0xffe00008 206 #define SH4_SCTDR 0xffe0000c 207 #define SH4_SCSSR 0xffe00010 208 #define SH4_SCRDR 0xffe00014 209 210 #define SH3_SCRSR /* can't access from CPU */ 211 #define SH3_SCTSR /* can't access from CPU */ 212 #define SH3_SCSMR 0xfffffe80 213 #define SH3_SCBRR 0xfffffe82 214 #define SH3_SCSCR 0xfffffe84 215 #define SH3_SCTDR 0xfffffe86 216 #define SH3_SCSSR 0xfffffe88 217 #define SH3_SCRDR 0xfffffe8a 218 #define SH3_SCPCR 0xa4000116 219 #define SH3_SCPDR 0xa4000136 220 221 #define SCSSR_TDRE 0x80 222 223 #define SH3_SCI_TX_BUSY() \ 224 while ((_reg_read_1(SH3_SCSSR) & SCSSR_TDRE) == 0) 225 226 #define SH3_SCI_PUTC(c) \ 227 __BEGIN_MACRO \ 228 SH3_SCI_TX_BUSY(); \ 229 _reg_write_1(SH3_SCTDR, c); \ 230 _reg_write_1(SH3_SCSSR, \ 231 _reg_read_1(SH3_SCSSR) & ~SCSSR_TDRE); \ 232 __END_MACRO 233 234 #define SH3_SCI_PRINT(s) \ 235 __BEGIN_MACRO \ 236 char *__s =(char *)(s); \ 237 int __i; \ 238 for (__i = 0; __s[__i] != '\0'; __i++) { \ 239 char __c = __s[__i]; \ 240 if (__c == '\n') \ 241 SH3_SCI_PUTC('\r'); \ 242 SH3_SCI_PUTC(__c); \ 243 } \ 244 __END_MACRO 245 246 /* 247 * SCIF 248 */ 249 #define SH4_SCSMR2 0xffe80000 250 #define SH4_SCBRR2 0xffe80004 251 #define SH4_SCSCR2 0xffe80008 252 #define SH4_SCFTDR2 0xffe8000c 253 #define SH4_SCFSR2 0xffe80010 254 #define SH4_SCFRDR2 0xffe80014 255 #define SH4_SCFCR2 0xffe80018 256 #define SH4_SCFDR2 0xffe8001c 257 #define SH4_SCSPTR2 0xffe80020 258 #define SH4_SCLSR2 0xffe80024 259 #define SH4_SCSMR2 0xffe80000 260 #define SH4_SCBRR2 0xffe80004 261 #define SH4_SCSCR2 0xffe80008 262 #define SH4_SCFTDR2 0xffe8000c 263 #define SH4_SCFSR2 0xffe80010 264 #define SH4_SCFRDR2 0xffe80014 265 #define SH4_SCFCR2 0xffe80018 266 #define SH4_SCFDR2 0xffe8001c 267 #define SH4_SCSPTR2 0xffe80020 268 #define SH4_SCLSR2 0xffe80024 269 270 #define SH4_SCSSR2 SH4_SCFSR2 271 #define SH4_SCSSR2 SH4_SCFSR2 272 273 #define SH3_SCSMR2 0xa4000150 /* R/W */ 274 #define SH3_SCBRR2 0xa4000152 /* R/W */ 275 #define SH3_SCSCR2 0xa4000154 /* R/W */ 276 #define SH3_SCFTDR2 0xa4000156 /* W */ 277 #define SH3_SCSSR2 0xa4000158 /* R/W(0 write only) */ 278 #define SH3_SCFRDR2 0xa400015a /* R */ 279 #define SH3_SCFCR2 0xa400015c /* R/W */ 280 #define SH3_SCFDR2 0xa400015e /* R */ 281 #define SH3_SCSMR2 0xa4000150 /* R/W */ 282 #define SH3_SCBRR2 0xa4000152 /* R/W */ 283 #define SH3_SCSCR2 0xa4000154 /* R/W */ 284 #define SH3_SCFTDR2 0xa4000156 /* W */ 285 #define SH3_SCSSR2 0xa4000158 /* R/W(0 write only) */ 286 #define SH3_SCFRDR2 0xa400015a /* R */ 287 #define SH3_SCFCR2 0xa400015c /* R/W */ 288 #define SH3_SCFDR2 0xa400015e /* R */ 289 290 #define SCSCR2_TIE 0x0080 /* Transmit Interrupt Enable */ 291 #define SCSCR2_RIE 0x0040 /* Receive Interrupt Enable */ 292 #define SCSCR2_TE 0x0020 /* Transmit Enable */ 293 #define SCSCR2_RE 0x0010 /* Receive Enable */ 294 #define SCSCR2_CKE1 0x0002 /* ClocK Enable 1 */ 295 #define SCSCR2_CKE0 0x0001 /* ClocK Enable 0 */ 296 #define SCSCR2_CKE 0x0003 /* ClocK Enable mask */ 297 298 #define SCSSR2_ER 0x0080 /* ERror */ 299 #define SCSSR2_TEND 0x0040 /* Transmit END */ 300 #define SCSSR2_TDFE 0x0020 /* Transmit Data Fifo Empty */ 301 #define SCSSR2_BRK 0x0010 /* BReaK detection */ 302 #define SCSSR2_FER 0x0008 /* Framing ERror */ 303 #define SCSSR2_PER 0x0004 /* Parity ERror */ 304 #define SCSSR2_RDF 0x0002 /* Receive fifo Data Full */ 305 #define SCSSR2_DR 0x0001 /* Data Ready */ 306 307 #define SCFCR2_RTRG1 0x0080 /* Receive TRiGger 1 */ 308 #define SCFCR2_RTRG0 0x0040 /* Receive TRiGger 0 */ 309 #define SCFCR2_TTRG1 0x0020 /* Transmit TRiGger 1 */ 310 #define SCFCR2_TTRG0 0x0010 /* Transmit TRiGger 0 */ 311 #define SCFCR2_MCE 0x0008 /* Modem Control Enable */ 312 #define SCFCR2_TFRST 0x0004 /* Transmit Fifo register ReSeT */ 313 #define SCFCR2_RFRST 0x0002 /* Receive Fifo register ReSeT */ 314 #define SCFCR2_LOOP 0x0001 /* LOOP back test */ 315 #define FIFO_RCV_TRIGGER_1 0x0000 316 #define FIFO_RCV_TRIGGER_4 0x0040 317 #define FIFO_RCV_TRIGGER_8 0x0080 318 #define FIFO_RCV_TRIGGER_14 0x00c0 319 #define FIFO_XMT_TRIGGER_8 0x0000 320 #define FIFO_XMT_TRIGGER_4 0x0010 321 #define FIFO_XMT_TRIGGER_2 0x0020 322 #define FIFO_XMT_TRIGGER_1 0x0030 323 324 #define SCFDR2_TXCNT 0xff00 /* Tx CouNT */ 325 #define SCFDR2_RECVCNT 0x00ff /* Rx CouNT */ 326 #define SCFDR2_TXF_FULL 0x1000 /* Tx FULL */ 327 #define SCFDR2_RXF_EPTY 0x0000 /* Rx EMPTY */ 328 329 #define SCSMR2_CHR 0x40 /* Character length */ 330 #define SCSMR2_PE 0x20 /* Parity enable */ 331 #define SCSMR2_OE 0x10 /* Parity mode */ 332 #define SCSMR2_STOP 0x08 /* Stop bit length */ 333 #define SCSMR2_CKS 0x03 /* Clock select */ 334 335 /* simple serial console macros. */ 336 #define SH3_SCIF_TX_BUSY() \ 337 while ((_reg_read_2(SH3_SCSSR2) & SCSSR2_TDFE) == 0) 338 339 #define SH3_SCIF_PUTC(c) \ 340 __BEGIN_MACRO \ 341 SH3_SCIF_TX_BUSY(); \ 342 /* wait until previous transmit done. */ \ 343 _reg_write_1(SH3_SCFTDR2, c); \ 344 /* Clear transmit FIFO empty flag */ \ 345 _reg_write_1(SH3_SCSSR2, \ 346 _reg_read_1(SH3_SCSSR2) & ~(SCSSR2_TDFE | SCSSR2_TEND)); \ 347 __END_MACRO 348 349 #define SH3_SCIF_PRINT(s) \ 350 __BEGIN_MACRO \ 351 char *__s =(char *)(s); \ 352 int __i; \ 353 for (__i = 0; __s[__i] != '\0'; __i++) { \ 354 char __c = __s[__i]; \ 355 if (__c == '\n') \ 356 SH3_SCIF_PUTC('\r'); \ 357 SH3_SCIF_PUTC(__c); \ 358 } \ 359 __END_MACRO 360 361 #define SH3_SCIF_PRINT_HEX(h) \ 362 __BEGIN_MACRO \ 363 uint32_t __h =(uint32_t)(h); \ 364 int __i; \ 365 SH3_SCIF_PUTC('0'); SH3_SCIF_PUTC('x'); \ 366 for (__i = 0; __i < 8; __i++, __h <<= 4) { \ 367 int __n =(__h >> 28) & 0xf; \ 368 char __c = __n > 9 ? 'A' + __n - 10 : '0' + __n; \ 369 SH3_SCIF_PUTC(__c); \ 370 } \ 371 SH3_SCIF_PUTC('\r'); SH3_SCIF_PUTC('\n'); \ 372 __END_MACRO 373 374 #endif /* _HPCBOOT_SH_DEV_SH_H_ */ 375
Indexes created Sat Sep 20 22:09:52 GMT 2025