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      1 /*	$NetBSD: bscreg.h,v 1.7 2008/02/17 05:36:38 uwe Exp $	*/
      2 
      3 /*-
      4  * Copyright (C) 1999 SAITOH Masanobu.  All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. The name of the author may not be used to endorse or promote products
     15  *    derived from this software without specific prior written permission.
     16  *
     17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     27  */
     28 
     29 #ifndef _SH3_BSCREG_H_
     30 #define	_SH3_BSCREG_H_
     31 #include <sh3/devreg.h>
     32 
     33 /*
     34  * Bus State Controller
     35  */
     36 
     37 #define	SH3_BCR1		0xffffff60	/* 16bit */
     38 #define	SH3_BCR2		0xffffff62	/* 16bit */
     39 #define	SH3_WCR1		0xffffff64	/* 16bit */
     40 #define	SH3_WCR2		0xffffff66	/* 16bit */
     41 #define	SH3_MCR			0xffffff68	/* 16bit */
     42 #define	SH3_DCR			0xffffff6a	/* 16bit */
     43 #define	SH3_PCR			0xffffff6c	/* 16bit */
     44 #define	SH3_RTCSR		0xffffff6e	/* 16bit */
     45 #define	SH3_RTCNT		0xffffff70	/* 16bit */
     46 #define	SH3_RTCOR		0xffffff72	/* 16bit */
     47 #define	SH3_RFCR		0xffffff74	/* 16bit */
     48 #define	SH3_BCR3		0xffffff7e	/* 16bit */
     49 
     50 #define	SH4_BCR1		0xff800000	/* 32bit */
     51 #define	SH4_BCR2		0xff800004	/* 16bit */
     52 #define	SH4_WCR1		0xff800008	/* 32bit */
     53 #define	SH4_WCR2		0xff80000c	/* 32bit */
     54 #define	SH4_WCR3		0xff800010	/* 32bit */
     55 #define	SH4_MCR			0xff800014	/* 32bit */
     56 #define	SH4_PCR			0xff800018	/* 16bit */
     57 #define	SH4_RTCSR		0xff80001c	/* 16bit */
     58 #define	SH4_RTCNT		0xff800020	/* 16bit */
     59 #define	SH4_RTCOR		0xff800024	/* 16bit */
     60 #define	SH4_RFCR		0xff800028	/* 16bit */
     61 #define	SH4_BCR3		0xff800050	/* 16bit: SH7751R */
     62 #define	SH4_BCR4		0xfe0a00f0	/* 32bit: SH7751R */
     63 
     64 #define	BCR1_MASTER		(1 << 30)
     65 #define	BCR1_BREQEN		(1 << 19)
     66 
     67 
     68 #define BCR2_AREA_WIDTH_MASK	0x3
     69 #define BCR2_AREA_WIDTH_8	0x1
     70 #define BCR2_AREA_WIDTH_16	0x2
     71 #define BCR2_AREA_WIDTH_32	0x3
     72 
     73 #define BCR2_AREA1_SHIFT	2
     74 #define BCR2_AREA2_SHIFT	4
     75 #define BCR2_AREA3_SHIFT	6
     76 #define BCR2_AREA4_SHIFT	8
     77 #define BCR2_AREA5_SHIFT	10
     78 #define BCR2_AREA6_SHIFT	12
     79 
     80 #define	BCR2_PORTEN		(1 << 0)
     81 
     82 #endif	/* !_SH3_BSCREG_H_ */
     83