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      1 /* $NetBSD: scifreg.h,v 1.12 2021/08/17 22:00:30 andvar Exp $ */
      2 
      3 /*-
      4  * Copyright (C) 1999 SAITOH Masanobu.  All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. The name of the author may not be used to endorse or promote products
     15  *    derived from this software without specific prior written permission.
     16  *
     17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     27  */
     28 
     29 #ifndef _SH3_SCIFREG_H_
     30 #define	_SH3_SCIFREG_H_
     31 
     32 /*
     33  * Serial Communication Interface with FIFO (SCIF)
     34  */
     35 
     36 #define SH3_SCIF0_BASE	0xa4000150
     37 #define SH3_SCIF1_BASE	0xa4000140
     38 
     39 #define SH4_SCIF_BASE	0xffe80000
     40 
     41 #ifdef SH3
     42 
     43 /* SH3 definitions */
     44 
     45 #define	SCIF_SMR		0x0	/* serial mode */
     46 #define	SCIF_BRR		0x2	/* bit rate */
     47 #define	SCIF_SCR		0x4	/* serial control */
     48 #define	SCIF_FTDR		0x6	/* transmit fifo data */
     49 #define	SCIF_SSR		0x8	/* serial status */
     50 #define	SCIF_FRDR		0xa	/* receive fifo data */
     51 #define	SCIF_FCR		0xc	/* fifo control */
     52 #define	SCIF_FDR		0xe	/* fifo data count set */
     53 
     54 #define	SHREG_SCSMR2  (*(volatile uint8_t  *)(SH3_SCIF0_BASE + SCIF_SMR))
     55 #define	SHREG_SCBRR2  (*(volatile uint8_t  *)(SH3_SCIF0_BASE + SCIF_BRR))
     56 #define	SHREG_SCSCR2  (*(volatile uint8_t  *)(SH3_SCIF0_BASE + SCIF_SCR))
     57 #define	SHREG_SCFTDR2 (*(volatile uint8_t  *)(SH3_SCIF0_BASE + SCIF_FTDR))
     58 #define	SHREG_SCSSR2  (*(volatile uint16_t *)(SH3_SCIF0_BASE + SCIF_SSR))
     59 #define	SHREG_SCFRDR2 (*(volatile uint8_t  *)(SH3_SCIF0_BASE + SCIF_FRDR))
     60 #define	SHREG_SCFCR2  (*(volatile uint8_t  *)(SH3_SCIF0_BASE + SCIF_FCR))
     61 #define	SHREG_SCFDR2  (*(volatile uint16_t *)(SH3_SCIF0_BASE + SCIF_FDR))
     62 
     63 #else  /* !SH3 */
     64 
     65 /* SH4 definitions */
     66 
     67 #define	SCIF_SMR		0x00	/* serial mode */
     68 #define	SCIF_BRR		0x04	/* bit rate */
     69 #define	SCIF_SCR		0x08	/* serial control */
     70 #define	SCIF_FTDR		0x0c	/* transmit fifo data */
     71 #define	SCIF_SSR		0x10	/* serial status */
     72 #define	SCIF_FRDR		0x14	/* receive fifo data */
     73 #define	SCIF_FCR		0x18	/* fifo control */
     74 #define	SCIF_FDR		0x1c	/* fifo data count set */
     75 
     76 #define SCIF_SPTR		0x20	/* serial port */
     77 #define SCIF_LSR		0x24	/* line status */
     78 
     79 #define	SHREG_SCSMR2  (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SMR))
     80 #define	SHREG_SCBRR2  (*(volatile uint8_t  *)(SH4_SCIF_BASE + SCIF_BRR))
     81 #define	SHREG_SCSCR2  (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SCR))
     82 #define	SHREG_SCFTDR2 (*(volatile uint8_t  *)(SH4_SCIF_BASE + SCIF_FTDR))
     83 #define	SHREG_SCSSR2  (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SSR))
     84 #define	SHREG_SCFRDR2 (*(volatile uint8_t  *)(SH4_SCIF_BASE + SCIF_FRDR))
     85 #define	SHREG_SCFCR2  (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_FCR))
     86 #define	SHREG_SCFDR2  (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_FDR))
     87 
     88 #define	SHREG_SCSPTR2 (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SPTR))
     89 #define	SHREG_SCLSR2  (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_LSR))
     90 
     91 /* alias */
     92 #define	SHREG_SCSFDR2	SHREG_SCFTDR2
     93 #define	SHREG_SCFSR2	SHREG_SCSSR2
     94 
     95 #define	SCSPTR2_RTSIO		0x0080
     96 #define	SCSPTR2_RTSDT		0x0040
     97 #define	SCSPTR2_CTSIO		0x0020
     98 #define	SCSPTR2_CTSDT		0x0010
     99 #define	SCSPTR2_SCKIO		0x0008
    100 #define	SCSPTR2_SCKDT		0x0004
    101 #define	SCSPTR2_SPB2IO		0x0002
    102 #define	SCSPTR2_SPB2DT		0x0001
    103 
    104 #define SCLSR2_ORER		0x0001	/* overrun error */
    105 
    106 #endif /* !SH3 */
    107 
    108 /* SMR: serial mode */
    109 #define SCSMR2_CHR		0x40	/* character width (set = 7bit) */
    110 #define SCSMR2_PE		0x20	/* Parity Enable */
    111 #define SCSMR2_O		0x10	/* parity mode Odd */
    112 #define SCSMR2_STOP		0x08	/* STOP bit (set = 2 stop bits) */
    113 #define	SCSMR2_CKS1		0x02	/* ClocK Select 1 */
    114 #define	SCSMR2_CKS0		0x01	/* ClocK Select 0 */
    115 
    116 /* SMR: serial mode (for IrDA) */
    117 #define SCSMR2_IRMOD		0x80	/* IrDA mode */
    118 #define SCSMR2_ICK3		0x40
    119 #define SCSMR2_ICK2		0x20
    120 #define SCSMR2_ICK1		0x10
    121 #define SCSMR2_ICK0		0x08
    122 #define SCSMR2_PSEL		0x04	/* Pulse width SELelect */
    123 
    124 /* SCR: serial control */
    125 #define	SCSCR2_TIE		0x80	/* Transmit Interrupt Enable */
    126 #define	SCSCR2_RIE		0x40	/* Receive Interrupt Enable */
    127 #define	SCSCR2_TE		0x20	/* Transmit Enable */
    128 #define	SCSCR2_RE		0x10	/* Receive Enable */
    129 #define	SCSCR2_CKE1		0x02	/* ClocK Enable 1 */
    130 #define	SCSCR2_CKE0		0x01	/* ClocK Enable 0 (not in sh4) */
    131 
    132 /* SSR: serial status */
    133 #define	SCSSR2_ER		0x0080	/* ERror */
    134 #define	SCSSR2_TEND		0x0040	/* Transmit END */
    135 #define	SCSSR2_TDFE		0x0020	/* Transmit Data Fifo Empty */
    136 #define	SCSSR2_BRK		0x0010	/* BReaK detection */
    137 #define	SCSSR2_FER		0x0008	/* Framing ERror */
    138 #define	SCSSR2_PER		0x0004	/* Parity ERror */
    139 #define	SCSSR2_RDF		0x0002	/* Receive fifo Data Full */
    140 #define	SCSSR2_DR		0x0001	/* Data Ready */
    141 
    142 /* FCR: fifo control */
    143 #define	SCFCR2_RTRG1		0x80	/* Receive TRiGger 1 */
    144 #define	SCFCR2_RTRG0		0x40	/* Receive TRiGger 0 */
    145 #define	SCFCR2_TTRG1		0x20	/* Transmit TRiGger 1 */
    146 #define	SCFCR2_TTRG0		0x10	/* Transmit TRiGger 0 */
    147 #define	SCFCR2_MCE		0x08	/* Modem Control Enable */
    148 #define	SCFCR2_TFRST		0x04	/* Transmit Fifo register ReSeT */
    149 #define	SCFCR2_RFRST		0x02	/* Receive Fifo register ReSeT */
    150 #define	SCFCR2_LOOP		0x01	/* LOOP back test */
    151 
    152 #define	FIFO_RCV_TRIGGER_1	0x00
    153 #define	FIFO_RCV_TRIGGER_4	0x40
    154 #define	FIFO_RCV_TRIGGER_8	0x80
    155 #define	FIFO_RCV_TRIGGER_14	0xc0
    156 
    157 #define	FIFO_XMT_TRIGGER_8	0x00
    158 #define	FIFO_XMT_TRIGGER_4	0x10
    159 #define	FIFO_XMT_TRIGGER_2	0x20
    160 #define	FIFO_XMT_TRIGGER_1	0x30
    161 
    162 /* FDR: fifo data count set */
    163 #define	SCFDR2_TXCNT		0xff00	/* Tx CouNT */
    164 #define	SCFDR2_RECVCNT		0x00ff	/* Rx CouNT */
    165 #define	SCFDR2_TXF_FULL		0x1000	/* Tx FULL */
    166 #define	SCFDR2_RXF_EPTY		0x0000	/* Rx EMPTY */
    167 
    168 #endif /* !_SH3_SCIFREG_ */
    169