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      1 /*	$NetBSD: gsreg.h,v 1.4 2014/03/31 11:25:49 martin Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2001 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by UCHIYAMA Yasushi.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #define GS_S_PMODE_REG		MIPS_PHYS_TO_KSEG1(0x12000000)
     33 #define GS_S_SMODE1_REG		MIPS_PHYS_TO_KSEG1(0x12000010)
     34 #define GS_S_SMODE2_REG		MIPS_PHYS_TO_KSEG1(0x12000020)
     35 #define GS_S_SRFSH_REG		MIPS_PHYS_TO_KSEG1(0x12000030)
     36 #define GS_S_SYNCH1_REG		MIPS_PHYS_TO_KSEG1(0x12000040)
     37 #define GS_S_SYNCH2_REG		MIPS_PHYS_TO_KSEG1(0x12000050)
     38 #define GS_S_SYNCV_REG		MIPS_PHYS_TO_KSEG1(0x12000060)
     39 #define GS_S_DISPFB1_REG	MIPS_PHYS_TO_KSEG1(0x12000070)
     40 #define GS_S_DISPLAY1_REG	MIPS_PHYS_TO_KSEG1(0x12000080)
     41 #define GS_S_DISPFB2_REG	MIPS_PHYS_TO_KSEG1(0x12000090)
     42 #define GS_S_DISPLAY2_REG	MIPS_PHYS_TO_KSEG1(0x120000a0)
     43 #define GS_S_EXTBUF_REG		MIPS_PHYS_TO_KSEG1(0x120000b0)
     44 #define GS_S_EXTDATA_REG	MIPS_PHYS_TO_KSEG1(0x120000c0)
     45 #define GS_S_EXTWRITE_REG	MIPS_PHYS_TO_KSEG1(0x120000d0)
     46 #define GS_S_BGCOLOR_REG	MIPS_PHYS_TO_KSEG1(0x120000e0)
     47 #define GS_S_CSR_REG		MIPS_PHYS_TO_KSEG1(0x12001000)
     48 #define GS_S_IMR_REG		MIPS_PHYS_TO_KSEG1(0x12001010)
     49 #define GS_S_BUSDIR_REG		MIPS_PHYS_TO_KSEG1(0x12001040)
     50 #define GS_S_SIGLBLID_REG	MIPS_PHYS_TO_KSEG1(0x12001080)
     51 
     52 #define SMODE1(vhp, vcksel, slck2, nvck, clksel, pevs, pehs, pvs, phs,	\
     53     gcont, spml, pck2, xpck, sint, prst, ex, cmod, slck, t1248, lc, rc)	\
     54 	(((u_int64_t)(vhp)	<< 36) |				\
     55 	((u_int64_t)(vcksel)	<< 34) |				\
     56 	((u_int64_t)(slck2)	<< 33) |				\
     57 	((u_int64_t)(nvck)	<< 32) |				\
     58 	((u_int64_t)(clksel)	<< 30) |				\
     59 	((u_int64_t)(pevs)	<< 29) |				\
     60 	((u_int64_t)(pehs)	<< 28) |				\
     61 	((u_int64_t)(pvs)	<< 27) |				\
     62 	((u_int64_t)(phs)	<< 26) |				\
     63 	((u_int64_t)(gcont)	<< 25) |				\
     64 	((u_int64_t)(spml)	<< 21) |				\
     65 	((u_int64_t)(pck2)	<< 19) |				\
     66 	((u_int64_t)(xpck)	<< 18) |				\
     67 	((u_int64_t)(sint)	<< 17) |				\
     68 	((u_int64_t)(prst)	<< 16) |				\
     69 	((u_int64_t)(ex)	<< 15) |				\
     70 	((u_int64_t)(cmod)	<< 13) |				\
     71 	((u_int64_t)(slck)	<< 12) |				\
     72 	((u_int64_t)(t1248)	<< 10) |				\
     73 	((u_int64_t)(lc)	<<  3) |				\
     74 	((u_int64_t)(rc)	<<  0))
     75 
     76 #define SMODE2(dpms, ffmd, inter)					\
     77 	(((u_int64_t)(dpms)	<< 2)	|				\
     78 	 ((u_int64_t)(ffmd)	<< 1)	|				\
     79 	 ((u_int64_t)(inter)	<< 0))
     80 
     81 #define SRFSH(x)	(x)
     82 
     83 #define SYNCH1(hs, hsvs, hseq, hbp, hfp)				\
     84 	(((u_int64_t)(hs)	<< 43) |				\
     85 	((u_int64_t)(hsvs)	<< 32) |				\
     86 	((u_int64_t)(hseq)	<< 22) |				\
     87 	((u_int64_t)(hbp)	<< 11) |				\
     88 	((u_int64_t)(hfp)	<< 0))
     89 
     90 #define SYNCH2(hb, hf)							\
     91 	(((u_int64_t)(hb)	<< 11) |				\
     92 	((u_int64_t)(hf)	<< 0))
     93 
     94 #define SYNCV(vs, vdp, vbpe, vbp, vfpe, vfp)				\
     95 	(((u_int64_t)(vs)	<< 53) |				\
     96 	((u_int64_t)(vdp)	<< 42) |				\
     97 	((u_int64_t)(vbpe)	<< 32) |				\
     98 	((u_int64_t)(vbp)	<< 20) |				\
     99 	((u_int64_t)(vfpe)	<< 10) |				\
    100 	((u_int64_t)(vfp)	<< 0))
    101 
    102 #define DISPLAY(dh, dw, magv, magh, dy, dx)				\
    103 	(((u_int64_t)(dh)	<< 44)	|				\
    104 	 ((u_int64_t)(dw)	<< 32)	|				\
    105 	 ((u_int64_t)(magv)	<< 27)	|				\
    106 	 ((u_int64_t)(magh)	<< 23)	|				\
    107 	 ((u_int64_t)(dy)	<< 12)	|				\
    108 	 ((u_int64_t)(dx)	<<  0))
    109