1 /* $NetBSD: smu71.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2 3 /* 4 * Copyright 2016 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef SMU71_H 26 #define SMU71_H 27 28 #if !defined(SMC_MICROCODE) 29 #pragma pack(push, 1) 30 #endif 31 32 #define SMU__NUM_PCIE_DPM_LEVELS 8 33 #define SMU__NUM_SCLK_DPM_STATE 8 34 #define SMU__NUM_MCLK_DPM_LEVELS 4 35 #define SMU__VARIANT__ICELAND 1 36 #define SMU__DGPU_ONLY 1 37 #define SMU__DYNAMIC_MCARB_SETTINGS 1 38 39 enum SID_OPTION { 40 SID_OPTION_HI, 41 SID_OPTION_LO, 42 SID_OPTION_COUNT 43 }; 44 45 typedef struct { 46 uint32_t high; 47 uint32_t low; 48 } data_64_t; 49 50 typedef struct { 51 data_64_t high; 52 data_64_t low; 53 } data_128_t; 54 55 #define SMU7_CONTEXT_ID_SMC 1 56 #define SMU7_CONTEXT_ID_VBIOS 2 57 58 #define SMU71_MAX_LEVELS_VDDC 8 59 #define SMU71_MAX_LEVELS_VDDCI 4 60 #define SMU71_MAX_LEVELS_MVDD 4 61 #define SMU71_MAX_LEVELS_VDDNB 8 62 63 #define SMU71_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE 64 #define SMU71_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS 65 #define SMU71_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS 66 #define SMU71_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS 67 #define SMU71_MAX_ENTRIES_SMIO 32 68 69 #define DPM_NO_LIMIT 0 70 #define DPM_NO_UP 1 71 #define DPM_GO_DOWN 2 72 #define DPM_GO_UP 3 73 74 #define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0 75 #define SMU7_FIRST_DPM_MEMORY_LEVEL 0 76 77 #define GPIO_CLAMP_MODE_VRHOT 1 78 #define GPIO_CLAMP_MODE_THERM 2 79 #define GPIO_CLAMP_MODE_DC 4 80 81 #define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0 82 #define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT) 83 #define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3 84 #define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT) 85 #define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6 86 #define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT) 87 #define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9 88 #define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT) 89 #define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12 90 #define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT) 91 #define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15 92 #define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT) 93 #define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18 94 #define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT) 95 #define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21 96 #define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT) 97 #define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24 98 #define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT) 99 #define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27 100 #define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT) 101 102 103 #if defined SMU__DGPU_ONLY 104 #define SMU71_DTE_ITERATIONS 5 105 #define SMU71_DTE_SOURCES 3 106 #define SMU71_DTE_SINKS 1 107 #define SMU71_NUM_CPU_TES 0 108 #define SMU71_NUM_GPU_TES 1 109 #define SMU71_NUM_NON_TES 2 110 111 #endif 112 113 #if defined SMU__FUSION_ONLY 114 #define SMU7_DTE_ITERATIONS 5 115 #define SMU7_DTE_SOURCES 5 116 #define SMU7_DTE_SINKS 3 117 #define SMU7_NUM_CPU_TES 2 118 #define SMU7_NUM_GPU_TES 1 119 #define SMU7_NUM_NON_TES 2 120 121 #endif 122 123 struct SMU71_PIDController 124 { 125 uint32_t Ki; 126 int32_t LFWindupUpperLim; 127 int32_t LFWindupLowerLim; 128 uint32_t StatePrecision; 129 uint32_t LfPrecision; 130 uint32_t LfOffset; 131 uint32_t MaxState; 132 uint32_t MaxLfFraction; 133 uint32_t StateShift; 134 }; 135 136 typedef struct SMU71_PIDController SMU71_PIDController; 137 138 struct SMU7_LocalDpmScoreboard 139 { 140 uint32_t PercentageBusy; 141 142 int32_t PIDError; 143 int32_t PIDIntegral; 144 int32_t PIDOutput; 145 146 uint32_t SigmaDeltaAccum; 147 uint32_t SigmaDeltaOutput; 148 uint32_t SigmaDeltaLevel; 149 150 uint32_t UtilizationSetpoint; 151 152 uint8_t TdpClampMode; 153 uint8_t TdcClampMode; 154 uint8_t ThermClampMode; 155 uint8_t VoltageBusy; 156 157 int8_t CurrLevel; 158 int8_t TargLevel; 159 uint8_t LevelChangeInProgress; 160 uint8_t UpHyst; 161 162 uint8_t DownHyst; 163 uint8_t VoltageDownHyst; 164 uint8_t DpmEnable; 165 uint8_t DpmRunning; 166 167 uint8_t DpmForce; 168 uint8_t DpmForceLevel; 169 uint8_t DisplayWatermark; 170 uint8_t McArbIndex; 171 172 uint32_t MinimumPerfSclk; 173 174 uint8_t AcpiReq; 175 uint8_t AcpiAck; 176 uint8_t GfxClkSlow; 177 uint8_t GpioClampMode; 178 179 uint8_t FpsFilterWeight; 180 uint8_t EnabledLevelsChange; 181 uint8_t DteClampMode; 182 uint8_t FpsClampMode; 183 184 uint16_t LevelResidencyCounters [SMU71_MAX_LEVELS_GRAPHICS]; 185 uint16_t LevelSwitchCounters [SMU71_MAX_LEVELS_GRAPHICS]; 186 187 void (*TargetStateCalculator)(uint8_t); 188 void (*SavedTargetStateCalculator)(uint8_t); 189 190 uint16_t AutoDpmInterval; 191 uint16_t AutoDpmRange; 192 193 uint8_t FpsEnabled; 194 uint8_t MaxPerfLevel; 195 uint8_t AllowLowClkInterruptToHost; 196 uint8_t FpsRunning; 197 198 uint32_t MaxAllowedFrequency; 199 }; 200 201 typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard; 202 203 #define SMU7_MAX_VOLTAGE_CLIENTS 12 204 205 struct SMU7_VoltageScoreboard 206 { 207 uint16_t CurrentVoltage; 208 uint16_t HighestVoltage; 209 uint16_t MaxVid; 210 uint8_t HighestVidOffset; 211 uint8_t CurrentVidOffset; 212 #if defined (SMU__DGPU_ONLY) 213 uint8_t CurrentPhases; 214 uint8_t HighestPhases; 215 #else 216 uint8_t AvsOffset; 217 uint8_t AvsOffsetApplied; 218 #endif 219 uint8_t ControllerBusy; 220 uint8_t CurrentVid; 221 uint16_t RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS]; 222 #if defined (SMU__DGPU_ONLY) 223 uint8_t RequestedPhases[SMU7_MAX_VOLTAGE_CLIENTS]; 224 #endif 225 uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS]; 226 uint8_t TargetIndex; 227 uint8_t Delay; 228 uint8_t ControllerEnable; 229 uint8_t ControllerRunning; 230 uint16_t CurrentStdVoltageHiSidd; 231 uint16_t CurrentStdVoltageLoSidd; 232 #if defined (SMU__DGPU_ONLY) 233 uint16_t RequestedVddci; 234 uint16_t CurrentVddci; 235 uint16_t HighestVddci; 236 uint8_t CurrentVddciVid; 237 uint8_t TargetVddciIndex; 238 #endif 239 }; 240 241 typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard; 242 243 // ------------------------------------------------------------------------------------------------------------------------- 244 #define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */ 245 246 struct SMU7_PCIeLinkSpeedScoreboard 247 { 248 uint8_t DpmEnable; 249 uint8_t DpmRunning; 250 uint8_t DpmForce; 251 uint8_t DpmForceLevel; 252 253 uint8_t CurrentLinkSpeed; 254 uint8_t EnabledLevelsChange; 255 uint16_t AutoDpmInterval; 256 257 uint16_t AutoDpmRange; 258 uint16_t AutoDpmCount; 259 260 uint8_t DpmMode; 261 uint8_t AcpiReq; 262 uint8_t AcpiAck; 263 uint8_t CurrentLinkLevel; 264 265 }; 266 267 typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard; 268 269 // -------------------------------------------------------- CAC table ------------------------------------------------------ 270 #define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16 271 #define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16 272 273 #define SMU7_SCALE_I 7 274 #define SMU7_SCALE_R 12 275 276 struct SMU7_PowerScoreboard 277 { 278 uint16_t MinVoltage; 279 uint16_t MaxVoltage; 280 281 uint32_t AvgGpuPower; 282 283 uint16_t VddcLeakagePower[SID_OPTION_COUNT]; 284 uint16_t VddcSclkConstantPower[SID_OPTION_COUNT]; 285 uint16_t VddcSclkDynamicPower[SID_OPTION_COUNT]; 286 uint16_t VddcNonSclkDynamicPower[SID_OPTION_COUNT]; 287 uint16_t VddcTotalPower[SID_OPTION_COUNT]; 288 uint16_t VddcTotalCurrent[SID_OPTION_COUNT]; 289 uint16_t VddcLoadVoltage[SID_OPTION_COUNT]; 290 uint16_t VddcNoLoadVoltage[SID_OPTION_COUNT]; 291 292 uint16_t DisplayPhyPower; 293 uint16_t PciePhyPower; 294 295 uint16_t VddciTotalPower; 296 uint16_t Vddr1TotalPower; 297 298 uint32_t RocPower; 299 300 uint32_t last_power; 301 uint32_t enableWinAvg; 302 303 uint32_t lkg_acc; 304 uint16_t VoltLkgeScaler; 305 uint16_t TempLkgeScaler; 306 307 uint32_t uvd_cac_dclk; 308 uint32_t uvd_cac_vclk; 309 uint32_t vce_cac_eclk; 310 uint32_t samu_cac_samclk; 311 uint32_t display_cac_dispclk; 312 uint32_t acp_cac_aclk; 313 uint32_t unb_cac; 314 315 uint32_t WinTime; 316 317 uint16_t GpuPwr_MAWt; 318 uint16_t FilteredVddcTotalPower; 319 320 uint8_t CalculationRepeats; 321 uint8_t WaterfallUp; 322 uint8_t WaterfallDown; 323 uint8_t WaterfallLimit; 324 }; 325 326 typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard; 327 328 // -------------------------------------------------------------------------------------------------- 329 330 struct SMU7_ThermalScoreboard 331 { 332 int16_t GpuLimit; 333 int16_t GpuHyst; 334 uint16_t CurrGnbTemp; 335 uint16_t FilteredGnbTemp; 336 uint8_t ControllerEnable; 337 uint8_t ControllerRunning; 338 uint8_t WaterfallUp; 339 uint8_t WaterfallDown; 340 uint8_t WaterfallLimit; 341 uint8_t padding[3]; 342 }; 343 344 typedef struct SMU7_ThermalScoreboard SMU7_ThermalScoreboard; 345 346 // For FeatureEnables: 347 #define SMU7_SCLK_DPM_CONFIG_MASK 0x01 348 #define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02 349 #define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04 350 #define SMU7_MCLK_DPM_CONFIG_MASK 0x08 351 #define SMU7_UVD_DPM_CONFIG_MASK 0x10 352 #define SMU7_VCE_DPM_CONFIG_MASK 0x20 353 #define SMU7_ACP_DPM_CONFIG_MASK 0x40 354 #define SMU7_SAMU_DPM_CONFIG_MASK 0x80 355 #define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100 356 357 #define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001 358 #define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002 359 #define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100 360 #define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200 361 #define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000 362 #define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000 363 364 // All 'soft registers' should be uint32_t. 365 struct SMU71_SoftRegisters 366 { 367 uint32_t RefClockFrequency; 368 uint32_t PmTimerPeriod; 369 uint32_t FeatureEnables; 370 #if defined (SMU__DGPU_ONLY) 371 uint32_t PreVBlankGap; 372 uint32_t VBlankTimeout; 373 uint32_t TrainTimeGap; 374 uint32_t MvddSwitchTime; 375 uint32_t LongestAcpiTrainTime; 376 uint32_t AcpiDelay; 377 uint32_t G5TrainTime; 378 uint32_t DelayMpllPwron; 379 uint32_t VoltageChangeTimeout; 380 #endif 381 uint32_t HandshakeDisables; 382 383 uint8_t DisplayPhy1Config; 384 uint8_t DisplayPhy2Config; 385 uint8_t DisplayPhy3Config; 386 uint8_t DisplayPhy4Config; 387 388 uint8_t DisplayPhy5Config; 389 uint8_t DisplayPhy6Config; 390 uint8_t DisplayPhy7Config; 391 uint8_t DisplayPhy8Config; 392 393 uint32_t AverageGraphicsActivity; 394 uint32_t AverageMemoryActivity; 395 uint32_t AverageGioActivity; 396 397 uint8_t SClkDpmEnabledLevels; 398 uint8_t MClkDpmEnabledLevels; 399 uint8_t LClkDpmEnabledLevels; 400 uint8_t PCIeDpmEnabledLevels; 401 402 uint32_t DRAM_LOG_ADDR_H; 403 uint32_t DRAM_LOG_ADDR_L; 404 uint32_t DRAM_LOG_PHY_ADDR_H; 405 uint32_t DRAM_LOG_PHY_ADDR_L; 406 uint32_t DRAM_LOG_BUFF_SIZE; 407 uint32_t UlvEnterCount; 408 uint32_t UlvTime; 409 uint32_t UcodeLoadStatus; 410 uint8_t DPMFreezeAndForced; 411 uint8_t Activity_Weight; 412 uint8_t Reserved8[2]; 413 uint32_t Reserved; 414 }; 415 416 typedef struct SMU71_SoftRegisters SMU71_SoftRegisters; 417 418 struct SMU71_Firmware_Header 419 { 420 uint32_t Digest[5]; 421 uint32_t Version; 422 uint32_t HeaderSize; 423 uint32_t Flags; 424 uint32_t EntryPoint; 425 uint32_t CodeSize; 426 uint32_t ImageSize; 427 428 uint32_t Rtos; 429 uint32_t SoftRegisters; 430 uint32_t DpmTable; 431 uint32_t FanTable; 432 uint32_t CacConfigTable; 433 uint32_t CacStatusTable; 434 435 uint32_t mcRegisterTable; 436 437 uint32_t mcArbDramTimingTable; 438 439 uint32_t PmFuseTable; 440 uint32_t Globals; 441 uint32_t UvdDpmTable; 442 uint32_t AcpDpmTable; 443 uint32_t VceDpmTable; 444 uint32_t SamuDpmTable; 445 uint32_t UlvSettings; 446 uint32_t Reserved[37]; 447 uint32_t Signature; 448 }; 449 450 typedef struct SMU71_Firmware_Header SMU71_Firmware_Header; 451 452 struct SMU7_HystController_Data 453 { 454 uint8_t waterfall_up; 455 uint8_t waterfall_down; 456 uint8_t pstate; 457 uint8_t clamp_mode; 458 }; 459 460 typedef struct SMU7_HystController_Data SMU7_HystController_Data; 461 462 #define SMU71_FIRMWARE_HEADER_LOCATION 0x20000 463 464 enum DisplayConfig { 465 PowerDown = 1, 466 DP54x4, 467 DP54x2, 468 DP54x1, 469 DP27x4, 470 DP27x2, 471 DP27x1, 472 HDMI297, 473 HDMI162, 474 LVDS, 475 DP324x4, 476 DP324x2, 477 DP324x1 478 }; 479 480 //#define SX_BLOCK_COUNT 8 481 //#define MC_BLOCK_COUNT 1 482 //#define CPL_BLOCK_COUNT 27 483 484 #if defined SMU__VARIANT__ICELAND 485 #define SX_BLOCK_COUNT 8 486 #define MC_BLOCK_COUNT 1 487 #define CPL_BLOCK_COUNT 29 488 #endif 489 490 struct SMU7_Local_Cac { 491 uint8_t BlockId; 492 uint8_t SignalId; 493 uint8_t Threshold; 494 uint8_t Padding; 495 }; 496 497 typedef struct SMU7_Local_Cac SMU7_Local_Cac; 498 499 struct SMU7_Local_Cac_Table { 500 SMU7_Local_Cac SxLocalCac[SX_BLOCK_COUNT]; 501 SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT]; 502 SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT]; 503 }; 504 505 typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table; 506 507 #if !defined(SMC_MICROCODE) 508 #pragma pack(pop) 509 #endif 510 511 #endif 512 513
Indexes created Tue Sep 30 20:09:53 GMT 2025