1 /* $NetBSD: smu72.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2 3 /* 4 * Copyright 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef SMU72_H 27 #define SMU72_H 28 29 #if !defined(SMC_MICROCODE) 30 #pragma pack(push, 1) 31 #endif 32 33 #define SMU__NUM_SCLK_DPM_STATE 8 34 #define SMU__NUM_MCLK_DPM_LEVELS 4 35 #define SMU__NUM_LCLK_DPM_LEVELS 8 36 #define SMU__NUM_PCIE_DPM_LEVELS 8 37 38 enum SID_OPTION { 39 SID_OPTION_HI, 40 SID_OPTION_LO, 41 SID_OPTION_COUNT 42 }; 43 44 enum Poly3rdOrderCoeff { 45 LEAKAGE_TEMPERATURE_SCALAR, 46 LEAKAGE_VOLTAGE_SCALAR, 47 DYNAMIC_VOLTAGE_SCALAR, 48 POLY_3RD_ORDER_COUNT 49 }; 50 51 struct SMU7_Poly3rdOrder_Data { 52 int32_t a; 53 int32_t b; 54 int32_t c; 55 int32_t d; 56 uint8_t a_shift; 57 uint8_t b_shift; 58 uint8_t c_shift; 59 uint8_t x_shift; 60 }; 61 62 typedef struct SMU7_Poly3rdOrder_Data SMU7_Poly3rdOrder_Data; 63 64 struct Power_Calculator_Data { 65 uint16_t NoLoadVoltage; 66 uint16_t LoadVoltage; 67 uint16_t Resistance; 68 uint16_t Temperature; 69 uint16_t BaseLeakage; 70 uint16_t LkgTempScalar; 71 uint16_t LkgVoltScalar; 72 uint16_t LkgAreaScalar; 73 uint16_t LkgPower; 74 uint16_t DynVoltScalar; 75 uint32_t Cac; 76 uint32_t DynPower; 77 uint32_t TotalCurrent; 78 uint32_t TotalPower; 79 }; 80 81 typedef struct Power_Calculator_Data PowerCalculatorData_t; 82 83 struct Gc_Cac_Weight_Data { 84 uint8_t index; 85 uint32_t value; 86 }; 87 88 typedef struct Gc_Cac_Weight_Data GcCacWeight_Data; 89 90 91 typedef struct { 92 uint32_t high; 93 uint32_t low; 94 } data_64_t; 95 96 typedef struct { 97 data_64_t high; 98 data_64_t low; 99 } data_128_t; 100 101 #define SMU7_CONTEXT_ID_SMC 1 102 #define SMU7_CONTEXT_ID_VBIOS 2 103 104 #define SMU72_MAX_LEVELS_VDDC 16 105 #define SMU72_MAX_LEVELS_VDDGFX 16 106 #define SMU72_MAX_LEVELS_VDDCI 8 107 #define SMU72_MAX_LEVELS_MVDD 4 108 109 #define SMU_MAX_SMIO_LEVELS 4 110 111 #define SMU72_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE /* SCLK + SQ DPM + ULV */ 112 #define SMU72_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS /* MCLK Levels DPM */ 113 #define SMU72_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS /* LCLK Levels */ 114 #define SMU72_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS /* PCIe speed and number of lanes. */ 115 #define SMU72_MAX_LEVELS_UVD 8 /* VCLK/DCLK levels for UVD. */ 116 #define SMU72_MAX_LEVELS_VCE 8 /* ECLK levels for VCE. */ 117 #define SMU72_MAX_LEVELS_ACP 8 /* ACLK levels for ACP. */ 118 #define SMU72_MAX_LEVELS_SAMU 8 /* SAMCLK levels for SAMU. */ 119 #define SMU72_MAX_ENTRIES_SMIO 32 /* Number of entries in SMIO table. */ 120 121 #define DPM_NO_LIMIT 0 122 #define DPM_NO_UP 1 123 #define DPM_GO_DOWN 2 124 #define DPM_GO_UP 3 125 126 #define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0 127 #define SMU7_FIRST_DPM_MEMORY_LEVEL 0 128 129 #define GPIO_CLAMP_MODE_VRHOT 1 130 #define GPIO_CLAMP_MODE_THERM 2 131 #define GPIO_CLAMP_MODE_DC 4 132 133 #define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0 134 #define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT) 135 #define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3 136 #define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT) 137 #define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6 138 #define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT) 139 #define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9 140 #define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT) 141 #define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12 142 #define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT) 143 #define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15 144 #define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT) 145 #define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18 146 #define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT) 147 #define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21 148 #define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT) 149 #define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24 150 #define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT) 151 #define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27 152 #define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT) 153 154 /* Virtualization Defines */ 155 #define CG_XDMA_MASK 0x1 156 #define CG_XDMA_SHIFT 0 157 #define CG_UVD_MASK 0x2 158 #define CG_UVD_SHIFT 1 159 #define CG_VCE_MASK 0x4 160 #define CG_VCE_SHIFT 2 161 #define CG_SAMU_MASK 0x8 162 #define CG_SAMU_SHIFT 3 163 #define CG_GFX_MASK 0x10 164 #define CG_GFX_SHIFT 4 165 #define CG_SDMA_MASK 0x20 166 #define CG_SDMA_SHIFT 5 167 #define CG_HDP_MASK 0x40 168 #define CG_HDP_SHIFT 6 169 #define CG_MC_MASK 0x80 170 #define CG_MC_SHIFT 7 171 #define CG_DRM_MASK 0x100 172 #define CG_DRM_SHIFT 8 173 #define CG_ROM_MASK 0x200 174 #define CG_ROM_SHIFT 9 175 #define CG_BIF_MASK 0x400 176 #define CG_BIF_SHIFT 10 177 178 #define SMU72_DTE_ITERATIONS 5 179 #define SMU72_DTE_SOURCES 3 180 #define SMU72_DTE_SINKS 1 181 #define SMU72_NUM_CPU_TES 0 182 #define SMU72_NUM_GPU_TES 1 183 #define SMU72_NUM_NON_TES 2 184 #define SMU72_DTE_FAN_SCALAR_MIN 0x100 185 #define SMU72_DTE_FAN_SCALAR_MAX 0x166 186 #define SMU72_DTE_FAN_TEMP_MAX 93 187 #define SMU72_DTE_FAN_TEMP_MIN 83 188 189 #if defined SMU__FUSION_ONLY 190 #define SMU7_DTE_ITERATIONS 5 191 #define SMU7_DTE_SOURCES 5 192 #define SMU7_DTE_SINKS 3 193 #define SMU7_NUM_CPU_TES 2 194 #define SMU7_NUM_GPU_TES 1 195 #define SMU7_NUM_NON_TES 2 196 #endif 197 198 struct SMU7_HystController_Data { 199 uint8_t waterfall_up; 200 uint8_t waterfall_down; 201 uint8_t waterfall_limit; 202 uint8_t spare; 203 uint16_t release_cnt; 204 uint16_t release_limit; 205 }; 206 207 typedef struct SMU7_HystController_Data SMU7_HystController_Data; 208 209 struct SMU72_PIDController { 210 uint32_t Ki; 211 int32_t LFWindupUpperLim; 212 int32_t LFWindupLowerLim; 213 uint32_t StatePrecision; 214 uint32_t LfPrecision; 215 uint32_t LfOffset; 216 uint32_t MaxState; 217 uint32_t MaxLfFraction; 218 uint32_t StateShift; 219 }; 220 221 typedef struct SMU72_PIDController SMU72_PIDController; 222 223 struct SMU7_LocalDpmScoreboard { 224 uint32_t PercentageBusy; 225 226 int32_t PIDError; 227 int32_t PIDIntegral; 228 int32_t PIDOutput; 229 230 uint32_t SigmaDeltaAccum; 231 uint32_t SigmaDeltaOutput; 232 uint32_t SigmaDeltaLevel; 233 234 uint32_t UtilizationSetpoint; 235 236 uint8_t TdpClampMode; 237 uint8_t TdcClampMode; 238 uint8_t ThermClampMode; 239 uint8_t VoltageBusy; 240 241 int8_t CurrLevel; 242 int8_t TargLevel; 243 uint8_t LevelChangeInProgress; 244 uint8_t UpHyst; 245 246 uint8_t DownHyst; 247 uint8_t VoltageDownHyst; 248 uint8_t DpmEnable; 249 uint8_t DpmRunning; 250 251 uint8_t DpmForce; 252 uint8_t DpmForceLevel; 253 uint8_t DisplayWatermark; 254 uint8_t McArbIndex; 255 256 uint32_t MinimumPerfSclk; 257 258 uint8_t AcpiReq; 259 uint8_t AcpiAck; 260 uint8_t GfxClkSlow; 261 uint8_t GpioClampMode; /* bit0 = VRHOT: bit1 = THERM: bit2 = DC */ 262 263 uint8_t FpsFilterWeight; 264 uint8_t EnabledLevelsChange; 265 uint8_t DteClampMode; 266 uint8_t FpsClampMode; 267 268 uint16_t LevelResidencyCounters[SMU72_MAX_LEVELS_GRAPHICS]; 269 uint16_t LevelSwitchCounters[SMU72_MAX_LEVELS_GRAPHICS]; 270 271 void (*TargetStateCalculator)(uint8_t); 272 void (*SavedTargetStateCalculator)(uint8_t); 273 274 uint16_t AutoDpmInterval; 275 uint16_t AutoDpmRange; 276 277 uint8_t FpsEnabled; 278 uint8_t MaxPerfLevel; 279 uint8_t AllowLowClkInterruptToHost; 280 uint8_t FpsRunning; 281 282 uint32_t MaxAllowedFrequency; 283 284 uint32_t FilteredSclkFrequency; 285 uint32_t LastSclkFrequency; 286 uint32_t FilteredSclkFrequencyCnt; 287 }; 288 289 typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard; 290 291 #define SMU7_MAX_VOLTAGE_CLIENTS 12 292 293 typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t); 294 295 struct SMU_VoltageLevel { 296 uint8_t Vddc; 297 uint8_t Vddci; 298 uint8_t VddGfx; 299 uint8_t Phases; 300 }; 301 302 typedef struct SMU_VoltageLevel SMU_VoltageLevel; 303 304 struct SMU7_VoltageScoreboard { 305 SMU_VoltageLevel CurrentVoltage; 306 SMU_VoltageLevel TargetVoltage; 307 uint16_t MaxVid; 308 uint8_t HighestVidOffset; 309 uint8_t CurrentVidOffset; 310 311 uint8_t ControllerBusy; 312 uint8_t CurrentVid; 313 uint8_t CurrentVddciVid; 314 uint8_t VddGfxShutdown; /* 0 = normal mode, 1 = shut down */ 315 316 SMU_VoltageLevel RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS]; 317 uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS]; 318 319 uint8_t TargetIndex; 320 uint8_t Delay; 321 uint8_t ControllerEnable; 322 uint8_t ControllerRunning; 323 uint16_t CurrentStdVoltageHiSidd; 324 uint16_t CurrentStdVoltageLoSidd; 325 uint8_t OverrideVoltage; 326 uint8_t VddcUseUlvOffset; 327 uint8_t VddGfxUseUlvOffset; 328 uint8_t padding; 329 330 VoltageChangeHandler_t ChangeVddc; 331 VoltageChangeHandler_t ChangeVddGfx; 332 VoltageChangeHandler_t ChangeVddci; 333 VoltageChangeHandler_t ChangePhase; 334 VoltageChangeHandler_t ChangeMvdd; 335 336 VoltageChangeHandler_t functionLinks[6]; 337 338 uint8_t *VddcFollower1; 339 uint8_t *VddcFollower2; 340 int16_t Driver_OD_RequestedVidOffset1; 341 int16_t Driver_OD_RequestedVidOffset2; 342 343 }; 344 345 typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard; 346 347 #define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */ 348 349 struct SMU7_PCIeLinkSpeedScoreboard { 350 uint8_t DpmEnable; 351 uint8_t DpmRunning; 352 uint8_t DpmForce; 353 uint8_t DpmForceLevel; 354 355 uint8_t CurrentLinkSpeed; 356 uint8_t EnabledLevelsChange; 357 uint16_t AutoDpmInterval; 358 359 uint16_t AutoDpmRange; 360 uint16_t AutoDpmCount; 361 362 uint8_t DpmMode; 363 uint8_t AcpiReq; 364 uint8_t AcpiAck; 365 uint8_t CurrentLinkLevel; 366 367 }; 368 369 typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard; 370 371 /* -------------------------------------------------------- CAC table ------------------------------------------------------ */ 372 #define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16 373 #define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16 374 #define SMU7_SCALE_I 7 375 #define SMU7_SCALE_R 12 376 377 struct SMU7_PowerScoreboard { 378 PowerCalculatorData_t VddGfxPowerData[SID_OPTION_COUNT]; 379 PowerCalculatorData_t VddcPowerData[SID_OPTION_COUNT]; 380 381 uint32_t TotalGpuPower; 382 uint32_t TdcCurrent; 383 384 uint16_t VddciTotalPower; 385 uint16_t sparesasfsdfd; 386 uint16_t Vddr1Power; 387 uint16_t RocPower; 388 389 uint16_t CalcMeasPowerBlend; 390 uint8_t SidOptionPower; 391 uint8_t SidOptionCurrent; 392 393 uint32_t WinTime; 394 395 uint16_t Telemetry_1_slope; 396 uint16_t Telemetry_2_slope; 397 int32_t Telemetry_1_offset; 398 int32_t Telemetry_2_offset; 399 400 uint32_t VddcCurrentTelemetry; 401 uint32_t VddGfxCurrentTelemetry; 402 uint32_t VddcPowerTelemetry; 403 uint32_t VddGfxPowerTelemetry; 404 uint32_t VddciPowerTelemetry; 405 406 uint32_t VddcPower; 407 uint32_t VddGfxPower; 408 uint32_t VddciPower; 409 410 uint32_t TelemetryCurrent[2]; 411 uint32_t TelemetryVoltage[2]; 412 uint32_t TelemetryPower[2]; 413 }; 414 415 typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard; 416 417 struct SMU7_ThermalScoreboard { 418 int16_t GpuLimit; 419 int16_t GpuHyst; 420 uint16_t CurrGnbTemp; 421 uint16_t FilteredGnbTemp; 422 423 uint8_t ControllerEnable; 424 uint8_t ControllerRunning; 425 uint8_t AutoTmonCalInterval; 426 uint8_t AutoTmonCalEnable; 427 428 uint8_t ThermalDpmEnabled; 429 uint8_t SclkEnabledMask; 430 uint8_t spare[2]; 431 int32_t temperature_gradient; 432 433 SMU7_HystController_Data HystControllerData; 434 int32_t WeightedSensorTemperature; 435 uint16_t TemperatureLimit[SMU72_MAX_LEVELS_GRAPHICS]; 436 uint32_t Alpha; 437 }; 438 439 typedef struct SMU7_ThermalScoreboard SMU7_ThermalScoreboard; 440 441 /* For FeatureEnables: */ 442 #define SMU7_SCLK_DPM_CONFIG_MASK 0x01 443 #define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02 444 #define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04 445 #define SMU7_MCLK_DPM_CONFIG_MASK 0x08 446 #define SMU7_UVD_DPM_CONFIG_MASK 0x10 447 #define SMU7_VCE_DPM_CONFIG_MASK 0x20 448 #define SMU7_ACP_DPM_CONFIG_MASK 0x40 449 #define SMU7_SAMU_DPM_CONFIG_MASK 0x80 450 #define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100 451 452 #define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001 453 #define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002 454 #define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100 455 #define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200 456 #define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000 457 #define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000 458 459 /* All 'soft registers' should be uint32_t. */ 460 struct SMU72_SoftRegisters { 461 uint32_t RefClockFrequency; 462 uint32_t PmTimerPeriod; 463 uint32_t FeatureEnables; 464 465 uint32_t PreVBlankGap; 466 uint32_t VBlankTimeout; 467 uint32_t TrainTimeGap; 468 469 uint32_t MvddSwitchTime; 470 uint32_t LongestAcpiTrainTime; 471 uint32_t AcpiDelay; 472 uint32_t G5TrainTime; 473 uint32_t DelayMpllPwron; 474 uint32_t VoltageChangeTimeout; 475 476 uint32_t HandshakeDisables; 477 478 uint8_t DisplayPhy1Config; 479 uint8_t DisplayPhy2Config; 480 uint8_t DisplayPhy3Config; 481 uint8_t DisplayPhy4Config; 482 483 uint8_t DisplayPhy5Config; 484 uint8_t DisplayPhy6Config; 485 uint8_t DisplayPhy7Config; 486 uint8_t DisplayPhy8Config; 487 488 uint32_t AverageGraphicsActivity; 489 uint32_t AverageMemoryActivity; 490 uint32_t AverageGioActivity; 491 492 uint8_t SClkDpmEnabledLevels; 493 uint8_t MClkDpmEnabledLevels; 494 uint8_t LClkDpmEnabledLevels; 495 uint8_t PCIeDpmEnabledLevels; 496 497 uint8_t UVDDpmEnabledLevels; 498 uint8_t SAMUDpmEnabledLevels; 499 uint8_t ACPDpmEnabledLevels; 500 uint8_t VCEDpmEnabledLevels; 501 502 uint32_t DRAM_LOG_ADDR_H; 503 uint32_t DRAM_LOG_ADDR_L; 504 uint32_t DRAM_LOG_PHY_ADDR_H; 505 uint32_t DRAM_LOG_PHY_ADDR_L; 506 uint32_t DRAM_LOG_BUFF_SIZE; 507 uint32_t UlvEnterCount; 508 uint32_t UlvTime; 509 uint32_t UcodeLoadStatus; 510 uint32_t Reserved[2]; 511 512 }; 513 514 typedef struct SMU72_SoftRegisters SMU72_SoftRegisters; 515 516 struct SMU72_Firmware_Header { 517 uint32_t Digest[5]; 518 uint32_t Version; 519 uint32_t HeaderSize; 520 uint32_t Flags; 521 uint32_t EntryPoint; 522 uint32_t CodeSize; 523 uint32_t ImageSize; 524 525 uint32_t Rtos; 526 uint32_t SoftRegisters; 527 uint32_t DpmTable; 528 uint32_t FanTable; 529 uint32_t CacConfigTable; 530 uint32_t CacStatusTable; 531 uint32_t mcRegisterTable; 532 uint32_t mcArbDramTimingTable; 533 uint32_t PmFuseTable; 534 uint32_t Globals; 535 uint32_t ClockStretcherTable; 536 uint32_t Reserved[41]; 537 uint32_t Signature; 538 }; 539 540 typedef struct SMU72_Firmware_Header SMU72_Firmware_Header; 541 542 #define SMU72_FIRMWARE_HEADER_LOCATION 0x20000 543 544 enum DisplayConfig { 545 PowerDown = 1, 546 DP54x4, 547 DP54x2, 548 DP54x1, 549 DP27x4, 550 DP27x2, 551 DP27x1, 552 HDMI297, 553 HDMI162, 554 LVDS, 555 DP324x4, 556 DP324x2, 557 DP324x1 558 }; 559 560 #define MC_BLOCK_COUNT 1 561 #define CPL_BLOCK_COUNT 5 562 #define SE_BLOCK_COUNT 15 563 #define GC_BLOCK_COUNT 24 564 565 struct SMU7_Local_Cac { 566 uint8_t BlockId; 567 uint8_t SignalId; 568 uint8_t Threshold; 569 uint8_t Padding; 570 }; 571 572 typedef struct SMU7_Local_Cac SMU7_Local_Cac; 573 574 struct SMU7_Local_Cac_Table { 575 SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT]; 576 SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT]; 577 SMU7_Local_Cac SeLocalCac[SE_BLOCK_COUNT]; 578 SMU7_Local_Cac GcLocalCac[GC_BLOCK_COUNT]; 579 }; 580 581 typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table; 582 583 #if !defined(SMC_MICROCODE) 584 #pragma pack(pop) 585 #endif 586 587 /* Description of Clock Gating bitmask for Tonga: */ 588 /* System Clock Gating */ 589 #define CG_SYS_BITMASK_FIRST_BIT 0 /* First bit of Sys CG bitmask */ 590 #define CG_SYS_BITMASK_LAST_BIT 9 /* Last bit of Sys CG bitmask */ 591 #define CG_SYS_BIF_MGLS_SHIFT 0 592 #define CG_SYS_ROM_SHIFT 1 593 #define CG_SYS_MC_MGCG_SHIFT 2 594 #define CG_SYS_MC_MGLS_SHIFT 3 595 #define CG_SYS_SDMA_MGCG_SHIFT 4 596 #define CG_SYS_SDMA_MGLS_SHIFT 5 597 #define CG_SYS_DRM_MGCG_SHIFT 6 598 #define CG_SYS_HDP_MGCG_SHIFT 7 599 #define CG_SYS_HDP_MGLS_SHIFT 8 600 #define CG_SYS_DRM_MGLS_SHIFT 9 601 602 #define CG_SYS_BIF_MGLS_MASK 0x1 603 #define CG_SYS_ROM_MASK 0x2 604 #define CG_SYS_MC_MGCG_MASK 0x4 605 #define CG_SYS_MC_MGLS_MASK 0x8 606 #define CG_SYS_SDMA_MGCG_MASK 0x10 607 #define CG_SYS_SDMA_MGLS_MASK 0x20 608 #define CG_SYS_DRM_MGCG_MASK 0x40 609 #define CG_SYS_HDP_MGCG_MASK 0x80 610 #define CG_SYS_HDP_MGLS_MASK 0x100 611 #define CG_SYS_DRM_MGLS_MASK 0x200 612 613 /* Graphics Clock Gating */ 614 #define CG_GFX_BITMASK_FIRST_BIT 16 /* First bit of Gfx CG bitmask */ 615 #define CG_GFX_BITMASK_LAST_BIT 20 /* Last bit of Gfx CG bitmask */ 616 #define CG_GFX_CGCG_SHIFT 16 617 #define CG_GFX_CGLS_SHIFT 17 618 #define CG_CPF_MGCG_SHIFT 18 619 #define CG_RLC_MGCG_SHIFT 19 620 #define CG_GFX_OTHERS_MGCG_SHIFT 20 621 622 #define CG_GFX_CGCG_MASK 0x00010000 623 #define CG_GFX_CGLS_MASK 0x00020000 624 #define CG_CPF_MGCG_MASK 0x00040000 625 #define CG_RLC_MGCG_MASK 0x00080000 626 #define CG_GFX_OTHERS_MGCG_MASK 0x00100000 627 628 /* Voltage Regulator Configuration */ 629 /* VR Config info is contained in dpmTable.VRConfig */ 630 631 #define VRCONF_VDDC_MASK 0x000000FF 632 #define VRCONF_VDDC_SHIFT 0 633 #define VRCONF_VDDGFX_MASK 0x0000FF00 634 #define VRCONF_VDDGFX_SHIFT 8 635 #define VRCONF_VDDCI_MASK 0x00FF0000 636 #define VRCONF_VDDCI_SHIFT 16 637 #define VRCONF_MVDD_MASK 0xFF000000 638 #define VRCONF_MVDD_SHIFT 24 639 640 #define VR_MERGED_WITH_VDDC 0 641 #define VR_SVI2_PLANE_1 1 642 #define VR_SVI2_PLANE_2 2 643 #define VR_SMIO_PATTERN_1 3 644 #define VR_SMIO_PATTERN_2 4 645 #define VR_STATIC_VOLTAGE 5 646 647 /* Clock Stretcher Configuration */ 648 649 #define CLOCK_STRETCHER_MAX_ENTRIES 0x4 650 #define CKS_LOOKUPTable_MAX_ENTRIES 0x4 651 652 /* The 'settings' field is subdivided in the following way: */ 653 #define CLOCK_STRETCHER_SETTING_DDT_MASK 0x01 654 #define CLOCK_STRETCHER_SETTING_DDT_SHIFT 0x0 655 #define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK 0x1E 656 #define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT 0x1 657 #define CLOCK_STRETCHER_SETTING_ENABLE_MASK 0x80 658 #define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT 0x7 659 660 struct SMU_ClockStretcherDataTableEntry { 661 uint8_t minVID; 662 uint8_t maxVID; 663 664 uint16_t setting; 665 }; 666 typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry; 667 668 struct SMU_ClockStretcherDataTable { 669 SMU_ClockStretcherDataTableEntry ClockStretcherDataTableEntry[CLOCK_STRETCHER_MAX_ENTRIES]; 670 }; 671 typedef struct SMU_ClockStretcherDataTable SMU_ClockStretcherDataTable; 672 673 struct SMU_CKS_LOOKUPTableEntry { 674 uint16_t minFreq; 675 uint16_t maxFreq; 676 677 uint8_t setting; 678 uint8_t padding[3]; 679 }; 680 typedef struct SMU_CKS_LOOKUPTableEntry SMU_CKS_LOOKUPTableEntry; 681 682 struct SMU_CKS_LOOKUPTable { 683 SMU_CKS_LOOKUPTableEntry CKS_LOOKUPTableEntry[CKS_LOOKUPTable_MAX_ENTRIES]; 684 }; 685 typedef struct SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTable; 686 687 #endif 688 689 690
Indexes created Sat Sep 20 22:09:52 GMT 2025