1 /* $NetBSD: smu_ucode_xfer_cz.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2 3 /* 4 * Copyright 2016 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 // CZ Ucode Loading Definitions 26 #ifndef SMU_UCODE_XFER_CZ_H 27 #define SMU_UCODE_XFER_CZ_H 28 29 #define NUM_JOBLIST_ENTRIES 32 30 31 #define TASK_TYPE_NO_ACTION 0 32 #define TASK_TYPE_UCODE_LOAD 1 33 #define TASK_TYPE_UCODE_SAVE 2 34 #define TASK_TYPE_REG_LOAD 3 35 #define TASK_TYPE_REG_SAVE 4 36 #define TASK_TYPE_INITIALIZE 5 37 38 #define TASK_ARG_REG_SMCIND 0 39 #define TASK_ARG_REG_MMIO 1 40 #define TASK_ARG_REG_FCH 2 41 #define TASK_ARG_REG_UNB 3 42 43 #define TASK_ARG_INIT_MM_PWR_LOG 0 44 #define TASK_ARG_INIT_CLK_TABLE 1 45 46 #define JOB_GFX_SAVE 0 47 #define JOB_GFX_RESTORE 1 48 #define JOB_FCH_SAVE 2 49 #define JOB_FCH_RESTORE 3 50 #define JOB_UNB_SAVE 4 51 #define JOB_UNB_RESTORE 5 52 #define JOB_GMC_SAVE 6 53 #define JOB_GMC_RESTORE 7 54 #define JOB_GNB_SAVE 8 55 #define JOB_GNB_RESTORE 9 56 57 #define IGNORE_JOB 0xff 58 #define END_OF_TASK_LIST (uint16_t)0xffff 59 60 // Size of DRAM regions (in bytes) requested by SMU: 61 #define SMU_DRAM_REQ_MM_PWR_LOG 48 62 63 #define UCODE_ID_SDMA0 0 64 #define UCODE_ID_SDMA1 1 65 #define UCODE_ID_CP_CE 2 66 #define UCODE_ID_CP_PFP 3 67 #define UCODE_ID_CP_ME 4 68 #define UCODE_ID_CP_MEC_JT1 5 69 #define UCODE_ID_CP_MEC_JT2 6 70 #define UCODE_ID_GMCON_RENG 7 71 #define UCODE_ID_RLC_G 8 72 #define UCODE_ID_RLC_SCRATCH 9 73 #define UCODE_ID_RLC_SRM_ARAM 10 74 #define UCODE_ID_RLC_SRM_DRAM 11 75 #define UCODE_ID_DMCU_ERAM 12 76 #define UCODE_ID_DMCU_IRAM 13 77 78 #define UCODE_ID_SDMA0_MASK 0x00000001 79 #define UCODE_ID_SDMA1_MASK 0x00000002 80 #define UCODE_ID_CP_CE_MASK 0x00000004 81 #define UCODE_ID_CP_PFP_MASK 0x00000008 82 #define UCODE_ID_CP_ME_MASK 0x00000010 83 #define UCODE_ID_CP_MEC_JT1_MASK 0x00000020 84 #define UCODE_ID_CP_MEC_JT2_MASK 0x00000040 85 #define UCODE_ID_GMCON_RENG_MASK 0x00000080 86 #define UCODE_ID_RLC_G_MASK 0x00000100 87 #define UCODE_ID_RLC_SCRATCH_MASK 0x00000200 88 #define UCODE_ID_RLC_SRM_ARAM_MASK 0x00000400 89 #define UCODE_ID_RLC_SRM_DRAM_MASK 0x00000800 90 #define UCODE_ID_DMCU_ERAM_MASK 0x00001000 91 #define UCODE_ID_DMCU_IRAM_MASK 0x00002000 92 93 #define UCODE_ID_SDMA0_SIZE_BYTE 10368 94 #define UCODE_ID_SDMA1_SIZE_BYTE 10368 95 #define UCODE_ID_CP_CE_SIZE_BYTE 8576 96 #define UCODE_ID_CP_PFP_SIZE_BYTE 16768 97 #define UCODE_ID_CP_ME_SIZE_BYTE 16768 98 #define UCODE_ID_CP_MEC_JT1_SIZE_BYTE 384 99 #define UCODE_ID_CP_MEC_JT2_SIZE_BYTE 384 100 #define UCODE_ID_GMCON_RENG_SIZE_BYTE 4096 101 #define UCODE_ID_RLC_G_SIZE_BYTE 2048 102 #define UCODE_ID_RLC_SCRATCH_SIZE_BYTE 132 103 #define UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE 8192 104 #define UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE 4096 105 #define UCODE_ID_DMCU_ERAM_SIZE_BYTE 24576 106 #define UCODE_ID_DMCU_IRAM_SIZE_BYTE 1024 107 108 #define NUM_UCODES 14 109 110 typedef struct { 111 uint32_t high; 112 uint32_t low; 113 } data_64_t; 114 115 struct SMU_Task { 116 uint8_t type; 117 uint8_t arg; 118 uint16_t next; 119 data_64_t addr; 120 uint32_t size_bytes; 121 }; 122 typedef struct SMU_Task SMU_Task; 123 124 struct TOC { 125 uint8_t JobList[NUM_JOBLIST_ENTRIES]; 126 SMU_Task tasks[1]; 127 }; 128 129 // META DATA COMMAND Definitions 130 #define METADATA_CMD_MODE0 0x00000103 131 #define METADATA_CMD_MODE1 0x00000113 132 #define METADATA_CMD_MODE2 0x00000123 133 #define METADATA_CMD_MODE3 0x00000133 134 #define METADATA_CMD_DELAY 0x00000203 135 #define METADATA_CMD_CHNG_REGSPACE 0x00000303 136 #define METADATA_PERFORM_ON_SAVE 0x00001000 137 #define METADATA_PERFORM_ON_LOAD 0x00002000 138 #define METADATA_CMD_ARG_MASK 0xFFFF0000 139 #define METADATA_CMD_ARG_SHIFT 16 140 141 // Simple register addr/data fields 142 struct SMU_MetaData_Mode0 { 143 uint32_t register_address; 144 uint32_t register_data; 145 }; 146 typedef struct SMU_MetaData_Mode0 SMU_MetaData_Mode0; 147 148 // Register addr/data with mask 149 struct SMU_MetaData_Mode1 { 150 uint32_t register_address; 151 uint32_t register_mask; 152 uint32_t register_data; 153 }; 154 typedef struct SMU_MetaData_Mode1 SMU_MetaData_Mode1; 155 156 struct SMU_MetaData_Mode2 { 157 uint32_t register_address; 158 uint32_t register_mask; 159 uint32_t target_value; 160 }; 161 typedef struct SMU_MetaData_Mode2 SMU_MetaData_Mode2; 162 163 // Always write data (even on a save operation) 164 struct SMU_MetaData_Mode3 { 165 uint32_t register_address; 166 uint32_t register_mask; 167 uint32_t register_data; 168 }; 169 typedef struct SMU_MetaData_Mode3 SMU_MetaData_Mode3; 170 171 #endif 172
Indexes created Fri Sep 26 08:10:20 GMT 2025