1 /* $NetBSD: dp83932reg.h,v 1.7 2008/04/28 20:23:49 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _DEV_IC_DP83932REG_H_ 33 #define _DEV_IC_DP83932REG_H_ 34 35 /* 36 * Register description for the National Semiconductor DP83932 37 * Systems-Oriented Network Interface Controller (SONIC). 38 */ 39 40 /* 41 * SONIC Receive Descriptor Area. 42 */ 43 struct sonic_rda16 { 44 uint16_t rda_status; 45 uint16_t rda_bytecount; 46 uint16_t rda_pkt_ptr0; 47 uint16_t rda_pkt_ptr1; 48 uint16_t rda_seqno; 49 uint16_t rda_link; 50 uint16_t rda_inuse; 51 } __packed; 52 53 struct sonic_rda32 { 54 uint32_t rda_status; 55 uint32_t rda_bytecount; 56 uint32_t rda_pkt_ptr0; 57 uint32_t rda_pkt_ptr1; 58 uint32_t rda_seqno; 59 uint32_t rda_link; 60 uint32_t rda_inuse; 61 } __packed; 62 63 #define RDA_SEQNO_RBA(x) (((x) >> 8) & 0xff) 64 #define RDA_SEQNO_RSN(x) ((x) & 0xff) 65 66 #define RDA_LINK_EOL 0x01 /* end-of-list */ 67 68 /* 69 * SONIC Receive Resource Area. 70 * 71 * Note, in 32-bit mode, Rx buffers must be aligned to 32-bit 72 * boundaries, and in 16-bit mode, to 16-bit boundaries. 73 * 74 * Also note the `word count' is always in units of 16-bit words. 75 */ 76 struct sonic_rra16 { 77 uint16_t rra_ptr0; 78 uint16_t rra_ptr1; 79 uint16_t rra_wc0; 80 uint16_t rra_wc1; 81 } __packed; 82 83 struct sonic_rra32 { 84 uint32_t rra_ptr0; 85 uint32_t rra_ptr1; 86 uint32_t rra_wc0; 87 uint32_t rra_wc1; 88 } __packed; 89 90 /* 91 * SONIC Transmit Descriptor Area 92 * 93 * Note the number of fragments defined here is arbitrary. 94 */ 95 #define SONIC_NTXFRAGS 16 96 97 struct sonic_frag16 { 98 uint16_t frag_ptr0; 99 uint16_t frag_ptr1; 100 uint16_t frag_size; 101 } __packed; 102 103 struct sonic_frag32 { 104 uint32_t frag_ptr0; 105 uint32_t frag_ptr1; 106 uint32_t frag_size; 107 } __packed; 108 109 /* 110 * Note the frag after the last frag is used to link up to the 111 * next descriptor. 112 */ 113 114 struct sonic_tda16 { 115 uint16_t tda_status; 116 uint16_t tda_pktconfig; 117 uint16_t tda_pktsize; 118 uint16_t tda_fragcnt; 119 struct sonic_frag16 tda_frags[SONIC_NTXFRAGS + 1]; 120 #if 0 121 uint16_t tda_link; 122 #endif 123 } __packed; 124 125 struct sonic_tda32 { 126 uint32_t tda_status; 127 uint32_t tda_pktconfig; 128 uint32_t tda_pktsize; 129 uint32_t tda_fragcnt; 130 struct sonic_frag32 tda_frags[SONIC_NTXFRAGS + 1]; 131 #if 0 132 uint32_t tda_link; 133 #endif 134 } __packed; 135 136 #define TDA_STATUS_NCOL(x) (((x) >> 11) & 0x1f) 137 138 #define TDA_LINK_EOL 0x01 /* end-of-list */ 139 140 /* 141 * SONIC CAM Descriptor Area. 142 */ 143 struct sonic_cda16 { 144 uint16_t cda_entry; 145 uint16_t cda_addr0; 146 uint16_t cda_addr1; 147 uint16_t cda_addr2; 148 } __packed; 149 150 struct sonic_cda32 { 151 uint32_t cda_entry; 152 uint32_t cda_addr0; 153 uint32_t cda_addr1; 154 uint32_t cda_addr2; 155 } __packed; 156 157 /* 158 * SONIC register file. 159 * 160 * NOTE: We define these as indices, and use a register map to deal 161 * with different address strides. 162 */ 163 164 #define SONIC_CR 0x00 /* Command Register */ 165 #define CR_HTX (1U << 0) /* Halt Transmission */ 166 #define CR_TXP (1U << 1) /* Transmit Packets */ 167 #define CR_RXDIS (1U << 2) /* Receiver Disable */ 168 #define CR_RXEN (1U << 3) /* Receiver Enable */ 169 #define CR_STP (1U << 4) /* Stop Timer */ 170 #define CR_ST (1U << 5) /* Start Timer */ 171 #define CR_RST (1U << 7) /* Software Reset */ 172 #define CR_RRRA (1U << 8) /* Read RRA */ 173 #define CR_LCAM (1U << 9) /* Load CAM */ 174 175 #define SONIC_DCR 0x01 /* Data Configuration Register */ 176 #define DCR_TFT0 (1U << 0) /* Transmit FIFO Threshold (lo) */ 177 #define DCR_TFT1 (1U << 1) /* Transmit FIFO Threshold (hi) */ 178 #define DCR_RFT0 (1U << 2) /* Receive FIFO Threshold (lo) */ 179 #define DCR_RFT1 (1U << 3) /* Receive FIFO Threshold (hi) */ 180 #define DCR_BMS (1U << 4) /* Block Mode Select for DMA */ 181 #define DCR_DW (1U << 5) /* Data Width Select */ 182 #define DCR_WC0 (1U << 6) /* Wait State Control (lo) */ 183 #define DCR_WC1 (1U << 7) /* Wait State Control (hi) */ 184 #define DCR_USR0 (1U << 8) /* User Definable Pin 0 */ 185 #define DCR_USR1 (1U << 9) /* User Definable Pin 1 */ 186 #define DCR_SBUS (1U << 10) /* Synchronous Bus Mode */ 187 #define DCR_PO0 (1U << 11) /* Programmable Output 0 */ 188 #define DCR_PO1 (1U << 12) /* Programmable Output 1 */ 189 #define DCR_LBR (1U << 13) /* Latched Bus Retry */ 190 #define DCR_EXBUS (1U << 15) /* Extended Bus Mode */ 191 192 #define SONIC_RCR 0x02 /* Receive Control Register */ 193 #define RCR_PRX (1U << 0) /* Packet Received OK */ 194 #define RCR_LBK (1U << 1) /* Loopback Packet Received */ 195 #define RCR_FAER (1U << 2) /* Frame Alignment Error */ 196 #define RCR_CRCR (1U << 3) /* CRC Error */ 197 #define RCR_COL (1U << 4) /* Collision Activity */ 198 #define RCR_CRS (1U << 5) /* Carrier Sense Activity */ 199 #define RCR_LPKT (1U << 6) /* Last Packet in RBA */ 200 #define RCR_BC (1U << 7) /* Broadcast Packet Received */ 201 #define RCR_MC (1U << 8) /* Multicast Packet Received */ 202 #define RCR_LB0 (1U << 9) /* Loopback Control 0 */ 203 #define RCR_LB1 (1U << 10) /* Loopback Control 1 */ 204 #define RCR_AMC (1U << 11) /* Accept All Multicast Packets */ 205 #define RCR_PRO (1U << 12) /* Physical Promiscuous Packets */ 206 #define RCR_BRD (1U << 13) /* Accept Broadcast Packets */ 207 #define RCR_RNT (1U << 14) /* Accept Runt Packets */ 208 #define RCR_ERR (1U << 15) /* Accept Packets with Errors */ 209 210 #define SONIC_TCR 0x03 /* Transmit Control Register */ 211 #define TCR_PTX (1U << 0) /* Packet Transmitted OK */ 212 #define TCR_BCM (1U << 1) /* Byte Count Mismatch */ 213 #define TCR_FU (1U << 2) /* FIFO Underrun */ 214 #define TCR_PMB (1U << 3) /* Packet Monitored Bad */ 215 #define TCR_OWC (1U << 5) /* Out of Window Collision */ 216 #define TCR_EXC (1U << 6) /* Excessive Collisions */ 217 #define TCR_CRSL (1U << 7) /* Carrier Sense Lost */ 218 #define TCR_NCRS (1U << 8) /* No Carrier Sense */ 219 #define TCR_DEF (1U << 9) /* Deferred Transmission */ 220 #define TCR_EXD (1U << 10) /* Excessive Deferral */ 221 #define TCR_EXDIS (1U << 12) /* Disable Excessive Deferral Timer */ 222 #define TCR_CRCI (1U << 13) /* CRC Inhibit */ 223 #define TCR_POWC (1U << 14) /* Programmed Out of Window Col. Tmr */ 224 #define TCR_PINT (1U << 15) /* Programmable Interrupt */ 225 226 #define SONIC_IMR 0x04 /* Interrupt Mask Register */ 227 #define IMR_RFO (1U << 0) /* Rx FIFO Overrun */ 228 #define IMR_MP (1U << 1) /* Missed Packet Tally */ 229 #define IMR_FAE (1U << 2) /* Frame Alignment Error Tally */ 230 #define IMR_CRC (1U << 3) /* CRC Tally */ 231 #define IMR_RBA (1U << 4) /* RBA Exceeded */ 232 #define IMR_RBE (1U << 5) /* Rx Buffers Exhausted */ 233 #define IMR_RDE (1U << 6) /* Rx Descriptors Exhausted */ 234 #define IMR_TC (1U << 7) /* Timer Complete */ 235 #define IMR_TXER (1U << 8) /* Transmit Error */ 236 #define IMR_PTX (1U << 9) /* Transmit OK */ 237 #define IMR_PRX (1U << 10) /* Packet Received */ 238 #define IMR_PINT (1U << 11) /* Programmable Interrupt */ 239 #define IMR_LCD (1U << 12) /* Load CAM Done */ 240 #define IMR_HBL (1U << 13) /* Heartbeat Lost */ 241 #define IMR_BR (1U << 14) /* Bus Retry Occurred */ 242 243 #define IMR_ALL 0x7fff 244 245 #define SONIC_ISR 0x05 /* Interrupt Status Register */ 246 /* See IMR bits. */ 247 248 #define SONIC_UTDAR 0x06 /* Upper Tx Descriptor Address Register */ 249 250 #define SONIC_CTDAR 0x07 /* Current Tx Descriptor Address Register */ 251 252 #define SONIC_TPS 0x08 /* Transmit Packet Size */ 253 254 #define SONIC_TFC 0x09 /* Transmit Fragment Count */ 255 256 #define SONIC_TSA0 0x0a /* Transmit Start Address (lo) */ 257 258 #define SONIC_TSA1 0x0b /* Transmit Start Address (hi) */ 259 260 #define SONIC_TFS 0x0c /* Transmit Fragment Size */ 261 262 #define SONIC_URDAR 0x0d /* Upper Rx Descriptor Address Register */ 263 264 #define SONIC_CRDAR 0x0e /* Current Rx Descriptor Address Register */ 265 266 #define SONIC_CRBA0 0x0f /* Current Receive Buffer Address (lo) */ 267 268 #define SONIC_CRBA1 0x10 /* Current Receive Buffer Address (hi) */ 269 270 #define SONIC_RBWC0 0x11 /* Remaining Buffer Word Count 0 */ 271 272 #define SONIC_RBWC1 0x12 /* Remaining Buffer Word Count 1 */ 273 274 #define SONIC_EOBC 0x13 /* End Of Buffer Word Count */ 275 276 #define SONIC_URRAR 0x14 /* Upper Rx Resource Address Register */ 277 278 #define SONIC_RSAR 0x15 /* Resource Start Address Register */ 279 280 #define SONIC_REAR 0x16 /* Resource End Address Register */ 281 282 #define SONIC_RRR 0x17 /* Resource Read Register */ 283 284 #define SONIC_RWR 0x18 /* Resource Write Register */ 285 286 #define SONIC_TRBA0 0x19 /* Temporary Receive Buffer Address (lo) */ 287 288 #define SONIC_TRBA1 0x1a /* Temporary Receive Buffer Address (hi) */ 289 290 #define SONIC_TBWC0 0x1b /* Temporary Buffer Word Count 0 */ 291 292 #define SONIC_TBWC1 0x1c /* Temporary Buffer Word Count 1 */ 293 294 #define SONIC_ADDR0 0x1d /* Address Generator 0 */ 295 296 #define SONIC_ADDR1 0x1e /* Address Generator 1 */ 297 298 #define SONIC_LLFA 0x1f /* Last Link Field Address */ 299 300 #define SONIC_TTDA 0x20 /* Temporary Tx Descriptor Address */ 301 302 #define SONIC_CEP 0x21 /* CAM Entry Pointer */ 303 304 #define SONIC_CAP2 0x22 /* CAM Address Port 2 */ 305 306 #define SONIC_CAP1 0x23 /* CAM Address Port 1 */ 307 308 #define SONIC_CAP0 0x24 /* CAM Address Port 0 */ 309 310 #define SONIC_CER 0x25 /* CAM Enable Register */ 311 312 #define SONIC_CDP 0x26 /* CAM Descriptor Pointer */ 313 314 #define SONIC_CDC 0x27 /* CAM Descriptor Count */ 315 316 #define SONIC_SRR 0x28 /* Silicon Revision Register */ 317 318 #define SONIC_WT0 0x29 /* Watchdog Timer 0 */ 319 320 #define SONIC_WT1 0x2a /* Watchdog Timer 1 */ 321 322 #define SONIC_RSC 0x2b /* Receive Sequence Counter */ 323 324 #define SONIC_CRCETC 0x2c /* CRC Error Tally Count */ 325 326 #define SONIC_FAET 0x2d /* Frame Alignment Error Tally */ 327 328 #define SONIC_MPT 0x2e /* Missed Packet Tally */ 329 330 #define SONIC_DCR2 0x3f /* Data Configuration Register 2 */ 331 #define DCR2_RJCM (1U << 0) /* Reject on CAM Match */ 332 #define DCR2_PCNM (1U << 1) /* Packet Compress When not Matched */ 333 #define DCR2_PCM (1U << 2) /* Packet Compress When Matched */ 334 #define DCR2_PH (1U << 4) /* Program Hold */ 335 #define DCR2_EXPO0 (1U << 12) /* Extended Programmable Output 0 */ 336 #define DCR2_EXPO1 (1U << 13) /* Extended Programmable Output 1 */ 337 #define DCR2_EXPO2 (1U << 14) /* Extended Programmable Output 2 */ 338 #define DCR2_EXPO3 (1U << 15) /* Extended Programmable Output 3 */ 339 340 #define SONIC_NREGS 0x40 341 342 #endif /* _DEV_IC_DP83932REG_H_ */ 343
Indexes created Sat Sep 20 22:09:52 GMT 2025