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    Searched defs:SOffset (Results 1 - 9 of 9) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
ARCISelLowering.cpp 292 SDValue SOffset = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
294 ISD::ADD, dl, getPointerTy(DAG.getDataLayout()), StackPtr, SOffset);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
GCNHazardRecognizer.cpp 728 // instruction is not using a register in the soffset field.
729 const MachineOperand *SOffset =
730 TII->getNamedOperand(MI, AMDGPU::OpName::soffset);
731 // If we have no soffset operand, then assume this field has been
734 (!SOffset || !SOffset->isReg()))
SILoadStoreOptimizer.cpp 88 bool SOffset = false;
435 Result.SOffset = true;
461 Result.SOffset = true;
551 if (Regs.SOffset)
553 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset);
1349 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset))
1413 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset))
1491 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset))
1644 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset))
SIRegisterInfo.cpp 758 MachineOperand *SOffset = TII->getNamedOperand(MI, AMDGPU::OpName::soffset);
759 assert(SOffset->isImm() && SOffset->getImm() == 0);
972 .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::soffset))
1039 MCRegister SOffset = ScratchOffsetReg;
1072 if (!IsOffsetLegal || (IsFlat && !SOffset && !ST.hasFlatScratchSTMode())) {
1073 SOffset = MCRegister();
1084 SOffset = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0, false);
1088 SOffset = Reg
    [all...]
AMDGPUISelDAGToDAG.cpp 190 SDValue &SOffset, SDValue &Offset, SDValue &Offen,
193 SDValue &SOffset, SDValue &Offset) const;
196 SDValue &SOffset, SDValue &ImmOffset) const;
198 SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
201 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
1389 SDValue &SOffset, SDValue &Offset,
1402 SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32);
1463 // Illegal offset, store it in soffset.
1465 SOffset =
1474 SDValue &VAddr, SDValue &SOffset,
    [all...]
AMDGPUInstructionSelector.cpp 2387 Register VAddr, RSrcReg, SOffset;
2391 if (selectMUBUFOffsetImpl(MI.getOperand(1), RSrcReg, SOffset, Offset)) {
2395 RSrcReg, SOffset, Offset)) {
2408 if (SOffset)
2409 MIB.addReg(SOffset);
2943 MachineOperand &SOffset = MI.getOperand(5);
2995 I.add(SOffset);
3724 [=](MachineInstrBuilder &MIB) { // soffset
3725 // Use constant zero for soffset and rely on eliminateFrameIndex
3769 [=](MachineInstrBuilder &MIB) { // soffset
    [all...]
AMDGPURegisterBankInfo.cpp 1329 // the three offsets (voffset, soffset and instoffset)
1339 uint32_t SOffset, ImmOffset;
1340 if (AMDGPU::splitMUBUFOffset(*Imm, SOffset, ImmOffset, &RBI.Subtarget,
1343 SOffsetReg = B.buildConstant(S32, SOffset).getReg(0);
1348 return SOffset + ImmOffset;
1358 uint32_t SOffset, ImmOffset;
1359 if ((int)Offset > 0 && AMDGPU::splitMUBUFOffset(Offset, SOffset, ImmOffset,
1363 SOffsetReg = B.buildConstant(S32, SOffset).getReg(0);
1369 // If we have SGPR base, we can use it for soffset.
1370 if (SOffset == 0)
    [all...]
SIInstrInfo.cpp 200 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
329 const MachineOperand *SOffset =
330 getNamedOperand(LdSt, AMDGPU::OpName::soffset);
331 if (SOffset) {
332 if (SOffset->isReg())
333 BaseOps.push_back(SOffset);
335 Offset += SOffset->getImm();
4180 // soffset register.
5624 MachineOperand *SOffset = getNamedOperand(MI, AMDGPU::OpName::soffset);
    [all...]
SIISelLowering.cpp 1281 // FIXME: Since we can split immediate into soffset and immediate offset,
6365 {}, // soffset
6732 // it returns the sum of VOffset, SOffset, and Offset.
6734 SDValue SOffset,
6738 if (!isa<ConstantSDNode>(VOffset) || !isa<ConstantSDNode>(SOffset) ||
6748 cast<ConstantSDNode>(SOffset)->getSExtValue() +
6765 Op.getOperand(5), // soffset
6792 Op.getOperand(6), // soffset
6921 SDValue(), // soffset -- will be set by setBufferOffsets
6963 Op.getOperand(4), // soffset
    [all...]

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