1 /* $NetBSD: spdmemreg.h,v 1.5 2022/01/29 08:14:24 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Paul Goyette 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* possible values for the memory type */ 32 #define SPDMEM_MEMTYPE_FPM 0x01 33 #define SPDMEM_MEMTYPE_EDO 0x02 34 #define SPDMEM_MEMTYPE_PIPE_NIBBLE 0x03 35 #define SPDMEM_MEMTYPE_SDRAM 0x04 36 #define SPDMEM_MEMTYPE_ROM 0x05 37 #define SPDMEM_MEMTYPE_DDRSGRAM 0x06 38 #define SPDMEM_MEMTYPE_DDRSDRAM 0x07 39 #define SPDMEM_MEMTYPE_DDR2SDRAM 0x08 40 #define SPDMEM_MEMTYPE_FBDIMM 0x09 41 #define SPDMEM_MEMTYPE_FBDIMM_PROBE 0x0A 42 #define SPDMEM_MEMTYPE_DDR3SDRAM 0x0B 43 #define SPDMEM_MEMTYPE_DDR4SDRAM 0x0C 44 #define SPDMEM_MEMTYPE_DDR4ESDRAM 0x0E 45 #define SPDMEM_MEMTYPE_LPDDR3SDRAM 0x0F 46 #define SPDMEM_MEMTYPE_LPDDR4SDRAM 0x10 47 #define SPDMEM_MEMTYPE_LPDDR4XSDRAM 0x11 48 #define SPDMEM_MEMTYPE_DDR5SDRAM 0x12 49 50 #define SPDMEM_MEMTYPE_RAMBUS 0x11 51 #define SPDMEM_MEMTYPE_DIRECTRAMBUS 0x01 52 53 /* Encodings of the size used/total byte for certain memory types */ 54 #define SPDMEM_SPDSIZE_MASK 0x0F /* SPD EEPROM Size */ 55 56 #define SPDMEM_SPDLEN_128 0x00 /* SPD EEPROM Sizes */ 57 #define SPDMEM_SPDLEN_176 0x10 58 #define SPDMEM_SPDLEN_256 0x20 59 #define SPDMEM_SPDLEN_MASK 0x70 /* Bits 4 - 6 */ 60 61 #define SPDMEM_SPDCRC_116 0x80 /* CRC Bytes covered */ 62 #define SPDMEM_SPDCRC_125 0x00 63 #define SPDMEM_SPDCRC_MASK 0x80 /* Bit 7 */ 64 65 /* possible values for the supply voltage */ 66 #define SPDMEM_VOLTAGE_TTL_5V 0x00 67 #define SPDMEM_VOLTAGE_TTL_LV 0x01 68 #define SPDMEM_VOLTAGE_HSTTL_1_5V 0x02 69 #define SPDMEM_VOLTAGE_SSTL_3_3V 0x03 70 #define SPDMEM_VOLTAGE_SSTL_2_5V 0x04 71 #define SPDMEM_VOLTAGE_SSTL_1_8V 0x05 72 73 /* possible values for module configuration */ 74 #define SPDMEM_MODCONFIG_PARITY 0x01 75 #define SPDMEM_MODCONFIG_ECC 0x02 76 77 /* for DDR2, module configuration is a bit-mask field */ 78 #define SPDMEM_MODCONFIG_HAS_DATA_PARITY 0x01 79 #define SPDMEM_MODCONFIG_HAS_DATA_ECC 0x02 80 #define SPDMEM_MODCONFIG_HAS_ADDR_CMD_PARITY 0x04 81 82 /* possible values for the refresh field */ 83 #define SPDMEM_REFRESH_STD 0x00 84 #define SPDMEM_REFRESH_QUARTER 0x01 85 #define SPDMEM_REFRESH_HALF 0x02 86 #define SPDMEM_REFRESH_TWOX 0x03 87 #define SPDMEM_REFRESH_FOURX 0x04 88 #define SPDMEM_REFRESH_EIGHTX 0x05 89 #define SPDMEM_REFRESH_SELFREFRESH 0x80 90 91 /* superset types */ 92 #define SPDMEM_SUPERSET_ESDRAM 0x01 93 #define SPDMEM_SUPERSET_DDR_ESDRAM 0x02 94 #define SPDMEM_SUPERSET_EDO_PEM 0x03 95 #define SPDMEM_SUPERSET_SDRAM_PEM 0x04 96 97 /* bit masks for "registered" module attribute */ 98 #define SPDMEM_SDR_MASK_REG 0x02 99 #define SPDMEM_DDR_MASK_REG 0x02 100 #define SPDMEM_DDR2_MASK_REG 0x05 101 102 #define SPDMEM_DDR3_TYPE_RDIMM 0x01 103 #define SPDMEM_DDR3_TYPE_UDIMM 0x02 104 #define SPDMEM_DDR3_TYPE_SODIMM 0x03 105 #define SPDMEM_DDR3_TYPE_MICRODIMM 0x04 106 #define SPDMEM_DDR3_TYPE_MINI_RDIMM 0x05 107 #define SPDMEM_DDR3_TYPE_MINI_UDIMM 0x06 108 109 #define SPDMEM_DDR4_TYPE_EXTENDED 0x00 110 #define SPDMEM_DDR4_TYPE_RDIMM 0x01 111 #define SPDMEM_DDR4_TYPE_UDIMM 0x02 112 #define SPDMEM_DDR4_TYPE_SODIMM 0x03 113 #define SPDMEM_DDR4_TYPE_LRDIMM 0x04 114 #define SPDMEM_DDR4_TYPE_MINI_RDIMM 0x05 115 #define SPDMEM_DDR4_TYPE_MINI_UDIMM 0x06 116 #define SPDMEM_DDR4_TYPE_RESERVED1 0x07 117 #define SPDMEM_DDR4_TYPE_72B_SO_RDIMM 0x08 118 #define SPDMEM_DDR4_TYPE_72B_SO_UDIMM 0x09 119 /* not defined 0x0a */ 120 #define SPDMEM_DDR4_TYPE_RESERVED2 0x0b 121 #define SPDMEM_DDR4_TYPE_16B_SO_DIMM 0x0c 122 #define SPDMEM_DDR4_TYPE_32B_SO_DIMM 0x0d 123 #define SPDMEM_DDR4_TYPE_RESERVED3 0x0e 124 /* not defined 0x0f */ 125
Indexes created Wed Oct 01 19:09:53 GMT 2025