| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsNaClELFStreamer.cpp | 136 unsigned SPReg = MI.getOperand(0).getReg();
137 assert((Mips::SP == SPReg) && "Unexpected stack-pointer register.");
138 emitMask(SPReg, LoadStoreStackMaskReg, STI);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86IndirectThunks.cpp | 245 const Register SPReg = Is64Bit ? X86::RSP : X86::ESP;
246 addRegOffset(BuildMI(CallTarget, DebugLoc(), TII->get(MovOpc)), SPReg, false,
|
| X86CallLowering.cpp | 96 auto SPReg =
101 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMCallLowering.cpp | 101 auto SPReg = MIRBuilder.buildCopy(p0, Register(ARM::SP));
105 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyFrameLowering.cpp | 229 unsigned SPReg = getSPReg(MF);
231 SPReg = MRI.createVirtualRegister(PtrRC);
235 BuildMI(MBB, InsertPt, DL, TII->get(getOpcGlobGet(MF)), SPReg)
244 .addReg(SPReg);
252 .addReg(SPReg)
292 unsigned SPReg = 0;
296 SPReg = FI->getBasePointerVreg();
306 SPReg = MRI.createVirtualRegister(PtrRC);
307 BuildMI(MBB, InsertPt, DL, TII->get(getOpcAdd(MF)), SPReg)
311 SPReg = SPFPReg
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| AArch64CallLowering.cpp | 252 if (!SPReg)
253 SPReg = MIRBuilder.buildCopy(p0, Register(AArch64::SP)).getReg(0);
257 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
328 Register SPReg;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsCallLowering.cpp | 266 auto SPReg = MIRBuilder.buildCopy(p0, Register(Mips::SP));
271 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVFrameLowering.cpp | 314 Register SPReg = getSPReg(STI);
325 BuildMI(MBB, MBBI, DL, TII->get(Opc), SPReg)
326 .addReg(SPReg)
339 Register SPReg = getSPReg(STI);
399 if (STI.isRegisterReservedByUser(SPReg))
411 adjustReg(MBB, MBBI, DL, SPReg, SPReg, -StackSize, MachineInstr::FrameSetup);
454 adjustReg(MBB, MBBI, DL, FPReg, SPReg,
470 adjustReg(MBB, MBBI, DL, SPReg, SPReg, -SecondSPAdjustAmount
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUCallLowering.cpp | 173 Register SPReg;
200 if (!SPReg)
201 SPReg = MIRBuilder.buildCopy(PtrTy, MFI->getStackPtrOffsetReg()).getReg(0);
205 auto AddrReg = MIRBuilder.buildPtrAdd(PtrTy, SPReg, OffsetReg);
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| SIFrameLowering.cpp | 484 Register SPReg = MFI->getStackPtrOffsetReg();
485 assert(SPReg != AMDGPU::SP_REG);
486 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), SPReg)
1294 Register SPReg = MFI->getStackPtrOffsetReg();
1297 BuildMI(MBB, I, DL, TII->get(Op), SPReg)
1298 .addReg(SPReg)
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| AMDGPURegisterBankInfo.cpp | 1271 Register SPReg = Info->getStackPtrOffsetReg();
1278 auto SPCopy = B.buildCopy(PtrTy, SPReg);
|
| SIISelLowering.cpp | 3277 Register SPReg = Info->getStackPtrOffsetReg();
3284 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
3306 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | 1023 Register SPReg = getStackPointerRegisterToSaveRestore();
1026 SDValue StackPointer = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i32);
1046 SDValue CopyChain = DAG.getCopyToReg(Chain, DL, SPReg, Sub);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 648 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
813 .addReg(SPReg);
827 .addReg(SPReg);
832 .addReg(SPReg);
837 .addReg(SPReg);
847 .addReg(SPReg);
865 .addReg(SPReg);
875 .addReg(SPReg);
888 .addReg(SPReg)
889 .addReg(SPReg);
[all...] |
| PPCISelLowering.cpp | 11692 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
11720 .addReg(SPReg)
11753 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::STDUX : PPC::STWUX), SPReg)
11755 .addReg(SPReg)
11763 .addReg(SPReg)
11776 BuildMI(BlockMBB, DL, TII->get(isPPC64 ? PPC::STDUX : PPC::STWUX), SPReg)
11778 .addReg(SPReg)
11794 .addReg(SPReg)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kISelLowering.cpp | 3217 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
3218 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
3221 SDValue SP = DAG.getCopyFromReg(Chain, DL, SPReg, VT);
3229 Chain = DAG.getCopyToReg(Chain, DL, SPReg, Result); // Output chain
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 2601 unsigned SPReg = SP::O6;
2602 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
2604 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 3444 Register SPReg = getStackPointerRegisterToSaveRestore();
3448 SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i64);
3471 Chain = DAG.getCopyToReg(Chain, DL, SPReg, NewSP);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 11580 /// ::= .setfp fpreg, spreg [, offset]
11597 // Parse spreg
11599 int SPReg = tryParseRegister();
11600 if (check(SPReg == -1, SPRegLoc, "stack pointer register expected") ||
11601 check(SPReg != ARM::SP && SPReg != UC.getFPReg(), SPRegLoc,
11631 static_cast<unsigned>(SPReg), Offset);
11921 int SPReg = tryParseRegister();
11922 if (SPReg == -1)
11924 if (SPReg == ARM::SP || SPReg == ARM::PC
[all...] |
