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Searched
defs:SR
(Results
1 - 25
of
95
) sorted by relevancy
1
2
3
4
/src/external/apache2/llvm/dist/llvm/lib/ExecutionEngine/JITLink/
DefineExternalSectionStartAndEndSymbols.h
52
auto &
SR
= getSectionRange(*D.Sec);
54
if (
SR
.empty())
57
G.makeDefined(*Sym, *
SR
.getFirstBlock(), 0, 0, Linkage::Strong,
60
if (
SR
.empty())
63
G.makeDefined(*Sym, *
SR
.getLastBlock(),
64
SR
.getLastBlock()->getSize(), 0, Linkage::Strong,
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce112/
amdgpu_dce112_clk_mgr.c
42
#define
SR
(reg_name)\
/src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Checkers/
MacOSXAPIChecker.cpp
56
const SubRegion *
SR
= dyn_cast<SubRegion>(R);
57
while (
SR
) {
58
if (const ObjCIvarRegion *IR = dyn_cast<ObjCIvarRegion>(
SR
))
60
SR
= dyn_cast<SubRegion>(
SR
->getSuperRegion());
CastSizeChecker.cpp
109
const SymbolicRegion *
SR
= dyn_cast<SymbolicRegion>(R);
110
if (!
SR
)
115
DefinedOrUnknownSVal Size = getDynamicExtent(state,
SR
, svalBuilder);
MIGChecker.cpp
136
const SymbolicRegion *
SR
= MR->getSymbolicBase();
137
if (!
SR
)
140
Sym =
SR
->getSymbol();
UnreachableCodeChecker.cpp
146
SourceRange
SR
;
158
SR
= S->getSourceRange();
161
if (
SR
.isInvalid() || !SL.isValid())
173
"This statement is never executed", DL,
SR
);
PointerArithChecker.cpp
70
void checkDeadSymbols(SymbolReaper &
SR
, CheckerContext &C) const;
76
void PointerArithChecker::checkDeadSymbols(SymbolReaper &
SR
,
84
if (!
SR
.isLiveRegion(I->first))
151
SourceRange
SR
= E->getSourceRange();
152
if (
SR
.isInvalid())
201
R->addRange(
SR
);
TestAfterDivZeroChecker.cpp
145
SymbolRef
SR
= Var.getAsSymbol();
146
if (!
SR
)
151
State->add<DivZeroMap>(ZeroState(
SR
, C.getBlockID(), C.getStackFrame()));
157
SymbolRef
SR
= Var.getAsSymbol();
158
if (!
SR
)
161
ZeroState ZS(
SR
, C.getBlockID(), C.getStackFrame());
ArrayBoundCheckerV2.cpp
73
const MemSpaceRegion *
SR
= region->getMemorySpace();
74
if (
SR
->getKind() == MemRegion::UnknownSpaceRegionKind)
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
dcn20_mmhubbub.h
41
#define
SR
(reg_name)\
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/
amdgpu_dce110_clk_mgr.c
40
#define
SR
(reg_name)\
/src/external/apache2/llvm/dist/clang/lib/Sema/
SemaDeclCXX.cpp
419
SourceRange
SR
;
421
SR
= SourceRange((*Toks)[1].getLocation(),
424
SR
= UnparsedDefaultArgLocs[Param];
426
<<
SR
;
/src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
RDFCopy.cpp
149
RegisterRef
SR
= FR->second;
150
if (DR ==
SR
)
153
NodeId AtCopy = getLocalReachingDef(
SR
, SA);
166
NodeId AtUse = getLocalReachingDef(
SR
, IA);
175
<< " with " << Print<RegisterRef>(
SR
, DFG) << " in "
179
unsigned NewReg = MinPhysReg(
SR
);
204
J.second =
SR
;
HexagonGenPredicate.cpp
475
RegisterSubReg
SR
= MI.getOperand(1);
478
if (!
SR
.R.isVirtual())
482
if (MRI->getRegClass(
SR
.R) != PredRC)
484
assert(!DR.S && !
SR
.S && "Unexpected subregister");
485
MRI->replaceRegWith(DR.R,
SR
.R);
HexagonVExtract.cpp
165
unsigned
SR
= ExtI->getOperand(1).getSubReg();
171
SR
== 0 ? 0 : VecSize/2);
/src/sys/dev/pci/
unichromemode.h
34
unsigned char
SR
[StdSR];
404
// unsigned char
SR
[StdSR];
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/
amdgpu_dcn20_clk_mgr.c
57
#define
SR
(reg_name)\
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_dwb.h
38
#define
SR
(reg_name)\
/src/external/apache2/llvm/dist/llvm/lib/CodeGen/
RDFRegisters.cpp
190
unsigned
SR
= SI.getSubReg();
191
if (!(MB[
SR
/32] & (1u << (
SR
%32))))
193
// The subregister
SR
is preserved.
RenameIndependentSubregs.cpp
69
LiveInterval::SubRange *
SR
;
72
SubRangeInfo(LiveIntervals &LIS, LiveInterval::SubRange &
SR
,
74
: ConEQ(LIS),
SR
(&
SR
), Index(Index) {}
161
for (LiveInterval::SubRange &
SR
: LI.subranges()) {
162
SubRangeInfos.push_back(SubRangeInfo(*LIS,
SR
, NumComponents));
165
unsigned NumSubComponents = ConEQ.Classify(
SR
);
186
const LiveInterval::SubRange &
SR
= *SRInfo.
SR
;
187
if ((
SR
.LaneMask & LaneMask).none()
[
all
...]
/src/external/apache2/llvm/dist/llvm/tools/llvm-objcopy/ELF/
ELFObjcopy.cpp
546
const SectionRename &
SR
= Iter->second;
547
Sec.Name = std::string(
SR
.NewName);
548
if (
SR
.NewFlags.hasValue())
549
setSectionFlagsAndType(Sec,
SR
.NewFlags.getValue());
/src/external/gpl3/binutils/dist/opcodes/
msp430-decode.c
89
#define
SR
(r) OP (1, MSP430_Operand_Register, r, 0)
155
PC SP
SR
CG
179
case 2: /* (
SR
) -> Absolute. */
208
SR
(reg);
219
case 2: /*
SR
-> Absolute. */
478
ID (MSO_rrc); DR (dstr);
SR
(dstr);
504
ID (MSO_mov);
SR
(srcr); DA ((dstr << 16) + IMMU(2));
528
ID (MSO_mov);
SR
(srcr); DM (dstr, IMMS(2));
651
ID (MSO_mov);
SR
(srcr); DR (dstr);
675
ID (MSO_cmp);
SR
(srcr); DR (dstr)
[
all
...]
rl78-decode.c
127
#define
SR
(r) OP (1, RL78_Operand_Register, RL78_Reg_##r, 0)
134
#define SCY()
SR
(PSW); SB(0)
295
ID(xch); DR(A);
SR
(X);
461
ID(mov); W(); DRW(ra);
SR
(AX);
496
ID(mov); DM(B, IMMU(2));
SR
(A);
701
ID(mov); DM(C, IMMU(2));
SR
(A);
871
ID(branch_cond_clear); DC(pc+IMMS(1)+3);
SR
(A); SB(bit); COND(T);
909
ID(branch_cond); DC(pc+IMMS(1)+3);
SR
(A); SB(bit); COND(T);
947
ID(branch_cond); DC(pc+IMMS(1)+3);
SR
(A); SB(bit); COND(F);
1486
ID(mov); DM(BC, IMMU(2));
SR
(A)
[
all
...]
/src/external/gpl3/binutils.old/dist/opcodes/
msp430-decode.c
89
#define
SR
(r) OP (1, MSP430_Operand_Register, r, 0)
155
PC SP
SR
CG
179
case 2: /* (
SR
) -> Absolute. */
208
SR
(reg);
219
case 2: /*
SR
-> Absolute. */
478
ID (MSO_rrc); DR (dstr);
SR
(dstr);
504
ID (MSO_mov);
SR
(srcr); DA ((dstr << 16) + IMMU(2));
528
ID (MSO_mov);
SR
(srcr); DM (dstr, IMMS(2));
651
ID (MSO_mov);
SR
(srcr); DR (dstr);
675
ID (MSO_cmp);
SR
(srcr); DR (dstr)
[
all
...]
rl78-decode.c
127
#define
SR
(r) OP (1, RL78_Operand_Register, RL78_Reg_##r, 0)
134
#define SCY()
SR
(PSW); SB(0)
295
ID(xch); DR(A);
SR
(X);
461
ID(mov); W(); DRW(ra);
SR
(AX);
496
ID(mov); DM(B, IMMU(2));
SR
(A);
701
ID(mov); DM(C, IMMU(2));
SR
(A);
871
ID(branch_cond_clear); DC(pc+IMMS(1)+3);
SR
(A); SB(bit); COND(T);
909
ID(branch_cond); DC(pc+IMMS(1)+3);
SR
(A); SB(bit); COND(T);
947
ID(branch_cond); DC(pc+IMMS(1)+3);
SR
(A); SB(bit); COND(F);
1486
ID(mov); DM(BC, IMMU(2));
SR
(A)
[
all
...]
Completed in 90 milliseconds
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Indexes created Sun Jun 07 00:24:08 UTC 2026