| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| dcn20_vmid.h | 39 #define SRI(reg_name, block, id)\
47 SRI(CNTL, DCN_VM_CONTEXT, id),\
48 SRI(PAGE_TABLE_BASE_ADDR_HI32, DCN_VM_CONTEXT, id),\
49 SRI(PAGE_TABLE_BASE_ADDR_LO32, DCN_VM_CONTEXT, id),\
50 SRI(PAGE_TABLE_START_ADDR_HI32, DCN_VM_CONTEXT, id),\
51 SRI(PAGE_TABLE_START_ADDR_LO32, DCN_VM_CONTEXT, id),\
52 SRI(PAGE_TABLE_END_ADDR_HI32, DCN_VM_CONTEXT, id),\
53 SRI(PAGE_TABLE_END_ADDR_LO32, DCN_VM_CONTEXT, id)
|
| dcn20_mmhubbub.h | 45 #define SRI(reg_name, block, id)\
62 SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
63 SRI(MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB, inst),\
64 SRI(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\
65 SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
66 SRI(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\
67 SRI(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\
68 SRI(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\
69 SRI(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\
70 SRI(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),
[all...] |
| dcn20_dwb.h | 43 #define SRI(reg_name, block, id)\
|
| amdgpu_dcn20_resource.c | 387 #define SRI(reg_name, block, id)\
560 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce112/ |
| amdgpu_dce112_clk_mgr.c | 46 #define SRI(reg_name, block, id)\
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/ |
| amdgpu_dce110_clk_mgr.c | 44 #define SRI(reg_name, block, id)\
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce120/ |
| amdgpu_irq_service_dce120.c | 105 #define SRI(reg_name, block, id)\
111 .enable_reg = SRI(reg1, block, reg_num),\
118 .ack_reg = SRI(reg2, block, reg_num),\
129 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
138 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
146 .status_reg = SRI(GRPH_INTERRUPT_STATUS, DCP, reg_num),\
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn10/ |
| amdgpu_irq_service_dcn10.c | 186 #define SRI(reg_name, block, id)\
192 .enable_reg = SRI(reg1, block, reg_num),\
199 .ack_reg = SRI(reg2, block, reg_num),\
210 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
219 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn20/ |
| amdgpu_irq_service_dcn20.c | 188 #define SRI(reg_name, block, id)\
194 .enable_reg = SRI(reg1, block, reg_num),\
201 .ack_reg = SRI(reg2, block, reg_num),\
214 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
223 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn21/ |
| amdgpu_irq_service_dcn21.c | 184 #define SRI(reg_name, block, id)\
190 .enable_reg = SRI(reg1, block, reg_num),\
197 .ack_reg = SRI(reg2, block, reg_num),\
210 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
219 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| dcn10_dwb.h | 42 #define SRI(reg_name, block, id)\
56 SRI(WB_ENABLE, CNV, inst),\
57 SRI(WB_EC_CONFIG, CNV, inst),\
58 SRI(CNV_MODE, CNV, inst),\
59 SRI(WB_SOFT_RESET, CNV, inst),\
60 SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
61 SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
62 SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
63 SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
64 SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),
[all...] |
| amdgpu_dcn10_resource.c | 180 #define SRI(reg_name, block, id)\
311 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/ |
| amdgpu_dce100_resource.c | 143 #define SRI(reg_name, block, id)\
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/ |
| amdgpu_dce112_resource.c | 153 #define SRI(reg_name, block, id)\
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| amdgpu_dce120_resource.c | 146 #define SRI(reg_name, block, id)\
264 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/ |
| amdgpu_dce80_resource.c | 160 #define SRI(reg_name, block, id)\
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_resource.c | 154 #define SRI(reg_name, block, id)\
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_resource.c | 298 #define SRI(reg_name, block, id)\
1519 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
|
