1 /* $NetBSD: trinityd.h,v 1.3 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Alex Deucher 25 */ 26 #ifndef _TRINITYD_H_ 27 #define _TRINITYD_H_ 28 29 /* pm registers */ 30 31 /* cg */ 32 #define CG_CGTT_LOCAL_0 0x0 33 #define CG_CGTT_LOCAL_1 0x1 34 35 /* smc */ 36 #define SMU_SCLK_DPM_STATE_0_CNTL_0 0x1f000 37 # define STATE_VALID(x) ((x) << 0) 38 # define STATE_VALID_MASK (0xff << 0) 39 # define STATE_VALID_SHIFT 0 40 # define CLK_DIVIDER(x) ((x) << 8) 41 # define CLK_DIVIDER_MASK (0xff << 8) 42 # define CLK_DIVIDER_SHIFT 8 43 # define VID(x) ((x) << 16) 44 # define VID_MASK (0xff << 16) 45 # define VID_SHIFT 16 46 # define LVRT(x) ((x) << 24) 47 # define LVRT_MASK (0xff << 24) 48 # define LVRT_SHIFT 24 49 #define SMU_SCLK_DPM_STATE_0_CNTL_1 0x1f004 50 # define DS_DIV(x) ((x) << 0) 51 # define DS_DIV_MASK (0xff << 0) 52 # define DS_DIV_SHIFT 0 53 # define DS_SH_DIV(x) ((x) << 8) 54 # define DS_SH_DIV_MASK (0xff << 8) 55 # define DS_SH_DIV_SHIFT 8 56 # define DISPLAY_WM(x) ((x) << 16) 57 # define DISPLAY_WM_MASK (0xff << 16) 58 # define DISPLAY_WM_SHIFT 16 59 # define VCE_WM(x) ((x) << 24) 60 # define VCE_WM_MASK (0xff << 24) 61 # define VCE_WM_SHIFT 24 62 63 #define SMU_SCLK_DPM_STATE_0_CNTL_3 0x1f00c 64 # define GNB_SLOW(x) ((x) << 0) 65 # define GNB_SLOW_MASK (0xff << 0) 66 # define GNB_SLOW_SHIFT 0 67 # define FORCE_NBPS1(x) ((x) << 8) 68 # define FORCE_NBPS1_MASK (0xff << 8) 69 # define FORCE_NBPS1_SHIFT 8 70 #define SMU_SCLK_DPM_STATE_0_AT 0x1f010 71 # define AT(x) ((x) << 0) 72 # define AT_MASK (0xff << 0) 73 # define AT_SHIFT 0 74 75 #define SMU_SCLK_DPM_STATE_0_PG_CNTL 0x1f014 76 # define PD_SCLK_DIVIDER(x) ((x) << 16) 77 # define PD_SCLK_DIVIDER_MASK (0xff << 16) 78 # define PD_SCLK_DIVIDER_SHIFT 16 79 80 #define SMU_SCLK_DPM_STATE_1_CNTL_0 0x1f020 81 82 #define SMU_SCLK_DPM_CNTL 0x1f100 83 # define SCLK_DPM_EN(x) ((x) << 0) 84 # define SCLK_DPM_EN_MASK (0xff << 0) 85 # define SCLK_DPM_EN_SHIFT 0 86 # define SCLK_DPM_BOOT_STATE(x) ((x) << 16) 87 # define SCLK_DPM_BOOT_STATE_MASK (0xff << 16) 88 # define SCLK_DPM_BOOT_STATE_SHIFT 16 89 # define VOLTAGE_CHG_EN(x) ((x) << 24) 90 # define VOLTAGE_CHG_EN_MASK (0xff << 24) 91 # define VOLTAGE_CHG_EN_SHIFT 24 92 93 #define SMU_SCLK_DPM_TT_CNTL 0x1f108 94 # define SCLK_TT_EN(x) ((x) << 0) 95 # define SCLK_TT_EN_MASK (0xff << 0) 96 # define SCLK_TT_EN_SHIFT 0 97 #define SMU_SCLK_DPM_TTT 0x1f10c 98 # define LT(x) ((x) << 0) 99 # define LT_MASK (0xffff << 0) 100 # define LT_SHIFT 0 101 # define HT(x) ((x) << 16) 102 # define HT_MASK (0xffff << 16) 103 # define HT_SHIFT 16 104 105 #define SMU_UVD_DPM_STATES 0x1f1a0 106 #define SMU_UVD_DPM_CNTL 0x1f1a4 107 108 #define SMU_S_PG_CNTL 0x1f118 109 # define DS_PG_EN(x) ((x) << 16) 110 # define DS_PG_EN_MASK (0xff << 16) 111 # define DS_PG_EN_SHIFT 16 112 113 #define GFX_POWER_GATING_CNTL 0x1f38c 114 # define PDS_DIV(x) ((x) << 0) 115 # define PDS_DIV_MASK (0xff << 0) 116 # define PDS_DIV_SHIFT 0 117 # define SSSD(x) ((x) << 8) 118 # define SSSD_MASK (0xff << 8) 119 # define SSSD_SHIFT 8 120 121 #define PM_CONFIG 0x1f428 122 # define SVI_Mode (1 << 29) 123 124 #define PM_I_CNTL_1 0x1f464 125 # define SCLK_DPM(x) ((x) << 0) 126 # define SCLK_DPM_MASK (0xff << 0) 127 # define SCLK_DPM_SHIFT 0 128 # define DS_PG_CNTL(x) ((x) << 16) 129 # define DS_PG_CNTL_MASK (0xff << 16) 130 # define DS_PG_CNTL_SHIFT 16 131 #define PM_TP 0x1f468 132 133 #define NB_PSTATE_CONFIG 0x1f5f8 134 # define Dpm0PgNbPsLo(x) ((x) << 0) 135 # define Dpm0PgNbPsLo_MASK (3 << 0) 136 # define Dpm0PgNbPsLo_SHIFT 0 137 # define Dpm0PgNbPsHi(x) ((x) << 2) 138 # define Dpm0PgNbPsHi_MASK (3 << 2) 139 # define Dpm0PgNbPsHi_SHIFT 2 140 # define DpmXNbPsLo(x) ((x) << 4) 141 # define DpmXNbPsLo_MASK (3 << 4) 142 # define DpmXNbPsLo_SHIFT 4 143 # define DpmXNbPsHi(x) ((x) << 6) 144 # define DpmXNbPsHi_MASK (3 << 6) 145 # define DpmXNbPsHi_SHIFT 6 146 147 #define DC_CAC_VALUE 0x1f908 148 149 #define GPU_CAC_AVRG_CNTL 0x1f920 150 # define WINDOW_SIZE(x) ((x) << 0) 151 # define WINDOW_SIZE_MASK (0xff << 0) 152 # define WINDOW_SIZE_SHIFT 0 153 154 #define CC_SMU_MISC_FUSES 0xe0001004 155 # define MinSClkDid(x) ((x) << 2) 156 # define MinSClkDid_MASK (0x7f << 2) 157 # define MinSClkDid_SHIFT 2 158 159 #define CC_SMU_TST_EFUSE1_MISC 0xe000101c 160 # define RB_BACKEND_DISABLE(x) ((x) << 16) 161 # define RB_BACKEND_DISABLE_MASK (3 << 16) 162 # define RB_BACKEND_DISABLE_SHIFT 16 163 164 #define SMU_SCRATCH_A 0xe0003024 165 166 #define SMU_SCRATCH0 0xe0003040 167 168 /* mmio */ 169 #define SMC_INT_REQ 0x220 170 171 #define SMC_MESSAGE_0 0x22c 172 #define SMC_RESP_0 0x230 173 174 #define GENERAL_PWRMGT 0x670 175 # define GLOBAL_PWRMGT_EN (1 << 0) 176 177 #define SCLK_PWRMGT_CNTL 0x678 178 # define DYN_PWR_DOWN_EN (1 << 2) 179 # define RESET_BUSY_CNT (1 << 4) 180 # define RESET_SCLK_CNT (1 << 5) 181 # define DYN_GFX_CLK_OFF_EN (1 << 7) 182 # define GFX_CLK_FORCE_ON (1 << 8) 183 # define DYNAMIC_PM_EN (1 << 21) 184 185 #define TARGET_AND_CURRENT_PROFILE_INDEX 0x684 186 # define TARGET_STATE(x) ((x) << 0) 187 # define TARGET_STATE_MASK (0xf << 0) 188 # define TARGET_STATE_SHIFT 0 189 # define CURRENT_STATE(x) ((x) << 4) 190 # define CURRENT_STATE_MASK (0xf << 4) 191 # define CURRENT_STATE_SHIFT 4 192 193 #define CG_GIPOTS 0x6d8 194 # define CG_GIPOT(x) ((x) << 16) 195 # define CG_GIPOT_MASK (0xffff << 16) 196 # define CG_GIPOT_SHIFT 16 197 198 #define CG_PG_CTRL 0x6e0 199 # define SP(x) ((x) << 0) 200 # define SP_MASK (0xffff << 0) 201 # define SP_SHIFT 0 202 # define SU(x) ((x) << 16) 203 # define SU_MASK (0xffff << 16) 204 # define SU_SHIFT 16 205 206 #define CG_MISC_REG 0x708 207 208 #define CG_THERMAL_INT_CTRL 0x738 209 # define DIG_THERM_INTH(x) ((x) << 0) 210 # define DIG_THERM_INTH_MASK (0xff << 0) 211 # define DIG_THERM_INTH_SHIFT 0 212 # define DIG_THERM_INTL(x) ((x) << 8) 213 # define DIG_THERM_INTL_MASK (0xff << 8) 214 # define DIG_THERM_INTL_SHIFT 8 215 # define THERM_INTH_MASK (1 << 24) 216 # define THERM_INTL_MASK (1 << 25) 217 218 #define CG_CG_VOLTAGE_CNTL 0x770 219 # define EN (1 << 9) 220 221 #define HW_REV 0x5564 222 # define ATI_REV_ID_MASK (0xf << 28) 223 # define ATI_REV_ID_SHIFT 28 224 /* 0 = A0, 1 = A1, 2 = B0, 3 = C0, etc. */ 225 226 #define CGTS_SM_CTRL_REG 0x9150 227 228 #define GB_ADDR_CONFIG 0x98f8 229 230 #endif 231
Indexes created Sat Sep 20 22:09:52 GMT 2025