| /src/crypto/external/bsd/openssl/dist/test/ |
| stack_test.c | 37 } SU;
42 DEFINE_STACK_OF_CONST(SU)
347 STACK_OF(SU) *s = sk_SU_new_null();
348 SU v[10];
360 TEST_info("SU stack size %d", i);
371 TEST_info("SU pointer check %d", i);
|
| /src/crypto/external/bsd/openssl.old/dist/test/ |
| stack_test.c | 37 } SU;
42 DEFINE_STACK_OF_CONST(SU)
339 STACK_OF(SU) *s = sk_SU_new_null();
340 SU v[10];
352 TEST_info("SU stack size %d", i);
363 TEST_info("SU pointer check %d", i);
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| MacroFusion.cpp | 39 static SUnit *getPredClusterSU(const SUnit &SU) {
40 for (const SDep &SI : SU.Preds)
47 static bool hasLessThanNumFused(const SUnit &SU, unsigned FuseLimit) {
49 const SUnit *CurrentSU = &SU;
101 SUnit *SU = SI.getSUnit();
103 SU == &DAG.ExitSU || SU == &SecondSU || SU->isPred(&SecondSU))
106 dbgs() << " - "; DAG.dumpNodeName(*SU); dbgs() << '\n';);
107 DAG.addEdge(SU, SDep(&SecondSU, SDep::Artificial))
[all...] |
| CriticalAntiDepBreaker.cpp | 139 /// CriticalPathStep - Return the next SUnit after SU on the bottom-up
141 static const SDep *CriticalPathStep(const SUnit *SU) {
145 for (const SDep &P : SU->Preds) {
459 const SUnit *SU = &SUnits[i];
460 MISUnitMap[SU->getInstr()] = SU;
461 if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency)
462 Max = SU;
662 // If the SU for the instruction being updated has debug informatio
[all...] |
| ScheduleDAGInstrs.cpp | 102 for (const SUnit *su : L) {
103 dbgs() << "SU(" << su->NodeNum << ")";
104 if (su != L.back())
231 /// MO is an operand of SU's instruction that defines a physical register. Adds
232 /// data dependencies from SU to any uses of the physical register.
233 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
234 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
242 const MCInstrDesc *DefMIDesc = &SU->getInstr()->getDesc();
248 SUnit *UseSU = I->SU;
[all...] |
| MachinePipeliner.cpp | 616 for (SUnit *SU : Schedule.getInstructions(Cycle)) {
617 OrderedInsts.push_back(SU->getInstr());
618 Cycles[SU->getInstr()] = Cycle;
619 Stages[SU->getInstr()] = Schedule.stageScheduled(SU);
691 const SUnit *SU = Worklist.pop_back_val();
692 for (auto &SI : SU->Succs) {
744 for (auto &SU : SUnits) {
745 MachineInstr &MI = *SU.getInstr();
755 SUs.push_back(&SU);
[all...] |
| MachineScheduler.cpp | 618 for (const SUnit *SU : Queue)
619 dbgs() << SU->NodeNum << " ";
637 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) {
654 // SU->TopReadyCycle was set to CurrCycle when it was scheduled. However,
656 if (SuccSU->TopReadyCycle < SU->TopReadyCycle + SuccEdge->getLatency())
657 SuccSU->TopReadyCycle = SU->TopReadyCycle + SuccEdge->getLatency();
664 /// releaseSuccessors - Call releaseSucc on each of SU's successors.
665 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) {
666 for (SDep &Succ : SU->Succs)
667 releaseSucc(SU, &Succ)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZMachineScheduler.h | 37 // DAG->getSchedClass(SU).
42 SUnit *SU = nullptr;
143 void schedNode(SUnit *SU, bool IsTopNode) override;
145 /// SU has had all predecessor dependencies resolved. Put it into
147 void releaseTopNode(SUnit *SU) override;
150 void releaseBottomNode(SUnit *SU) override {};
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.cpp | 79 SUnit *SU = &SUnits.back();
84 SU->SchedulingPref = Sched::None;
86 SU->SchedulingPref = TLI.getSchedulingPreference(N);
87 return SU;
91 SUnit *SU = newSUnit(Old->getNode());
92 SU->OrigNode = Old->OrigNode;
93 SU->Latency = Old->Latency;
94 SU->isVRegCycle = Old->isVRegCycle;
95 SU->isCall = Old->isCall;
96 SU->isCallOp = Old->isCallOp
[all...] |
| ResourcePriorityQueue.cpp | 71 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) {
73 for (SDep &Pred : SU->Preds) {
108 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU,
111 for (const SDep &Succ : SU->Succs) {
146 static unsigned numberCtrlDepsInSU(SUnit *SU) {
148 for (const SDep &Succ : SU->Succs)
155 static unsigned numberCtrlPredInSU(SUnit *SU) {
157 for (SDep &Pred : SU->Preds)
172 SUnit *SU = &(*SUnits)[i];
173 initNumRegDefsLeft(SU);
[all...] |
| ScheduleDAGRRList.cpp | 211 /// IsReachable - Checks if SU is reachable from TargetSU.
212 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) {
213 return Topo.IsReachable(SU, TargetSU);
216 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will
218 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) {
219 return Topo.WillCreateCycle(SU, TargetSU);
222 /// AddPredQueued - Queues and update to add a predecessor edge to SUnit SU.
225 void AddPredQueued(SUnit *SU, const SDep &D) {
226 Topo.AddPredQueued(SU, D.getSUnit());
227 SU->addPred(D)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| GCNMinRegStrategy.cpp | 25 const SUnit *SU;
29 : SU(SU_), Priority(Priority_) {}
38 bool isScheduled(const SUnit *SU) const {
39 assert(!SU->isBoundaryNode());
40 return NumPreds[SU->NodeNum] == std::numeric_limits<unsigned>::max();
43 void setIsScheduled(const SUnit *SU) {
44 assert(!SU->isBoundaryNode());
45 NumPreds[SU->NodeNum] = std::numeric_limits<unsigned>::max();
48 unsigned getNumPreds(const SUnit *SU) const {
49 assert(!SU->isBoundaryNode())
[all...] |
| GCNILPSched.cpp | 23 SUnit *SU;
26 : SU(SU_) {}
40 unsigned getNodePriority(const SUnit *SU) const;
47 void releasePredecessors(const SUnit* SU);
58 CalcNodeSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) {
59 unsigned &SethiUllmanNumber = SUNumbers[SU->NodeNum];
64 for (const SDep &Pred : SU->Preds) {
86 unsigned GCNILPScheduler::getNodePriority(const SUnit *SU) const {
87 assert(SU->NodeNum < SUNumbers.size());
88 if (SU->NumSuccs == 0 && SU->NumPreds != 0
[all...] |
| GCNSchedStrategy.cpp | 57 void GCNMaxOccupancySchedStrategy::initCandidate(SchedCandidate &Cand, SUnit *SU,
63 Cand.SU = SU;
74 TempTracker.getDownwardPressure(SU->getInstr(), Pressure, MaxPressure);
77 // and can be retrieved by DAG->getPressureDif(SU).
78 TempTracker.getUpwardPressure(SU->getInstr(), Pressure, MaxPressure);
151 for (SUnit *SU : Q) {
154 initCandidate(TryCand, SU, Zone.isTop(), RPTracker, SRI,
174 if (SUnit *SU = Bot.pickOnlyChoice()) {
176 return SU;
[all...] |
| R600MachineScheduler.cpp | 53 SUnit *SU = nullptr;
93 if (!SU && ((AllowSwitchToAlu && CurInstKind != IDAlu) ||
96 SU = pickAlu();
97 if (!SU && !PhysicalRegCopy.empty()) {
98 SU = PhysicalRegCopy.front();
101 if (SU) {
108 if (!SU) {
110 SU = pickOther(IDFetch);
111 if (SU)
116 if (!SU) {
[all...] |
| SIMachineScheduler.cpp | 178 void SIScheduleBlock::addUnit(SUnit *SU) {
179 NodeNum2Index[SU->NodeNum] = SUnits.size();
180 SUnits.push_back(SU);
186 dbgs() << " SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason);
238 if (TryCand.SU->NodeNum < Cand.SU->NodeNum) {
246 for (SUnit* SU : TopReadySUs) {
251 TryCand.SU = SU;
[all...] |
| SIMachineScheduler.h | 111 void addUnit(SUnit *SU);
116 // Add block pred, which has instruction predecessor of SU.
169 SUnit *SU = nullptr;
179 bool isValid() const { return SU; }
184 SU = Best.SU;
196 void undoReleaseSucc(SUnit *SU, SDep *SuccEdge);
197 void releaseSucc(SUnit *SU, SDep *SuccEdge);
200 void releaseSuccessors(SUnit *SU, bool InOrOutBlock);
202 void nodeScheduled(SUnit *SU);
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ScheduleDAGInstrs.h | 55 SUnit *SU;
57 VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU)
58 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
70 unsigned OperandIndex, SUnit *SU)
71 : VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {}
77 SUnit *SU;
81 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {
[all...] |
| MachineScheduler.h | 251 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
255 virtual void releaseTopNode(SUnit *SU) = 0;
259 virtual void releaseBottomNode(SUnit *SU) = 0;
363 void updateQueues(SUnit *SU, bool IsTopNode);
377 void releaseSucc(SUnit *SU, SDep *SuccEdge);
378 void releaseSuccessors(SUnit *SU);
379 void releasePred(SUnit *SU, SDep *PredEdge);
380 void releasePredecessors(SUnit *SU);
399 // Map each SU to its summary of pressure changes. This array is updated for
457 PressureDiff &getPressureDiff(const SUnit *SU) {
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonMachineScheduler.h | 81 bool isResourceAvailable(SUnit *SU, bool IsTop);
82 bool reserveResources(SUnit *SU, bool IsTop);
84 bool isInPacket(SUnit *SU) const { return is_contained(Packet, SU); }
115 SUnit *SU = nullptr;
185 for (auto &SU : DAG->SUnits)
186 MaxPath = std::max(MaxPath, isTop() ? SU.getHeight() : SU.getDepth());
195 bool checkHazard(SUnit *SU);
197 void releaseNode(SUnit *SU, unsigned ReadyCycle)
[all...] |
| HexagonMachineScheduler.cpp | 92 /// Check if scheduling of this SU is possible
97 bool VLIWResourceModel::isResourceAvailable(SUnit *SU, bool IsTop) {
98 if (!SU || !SU->getInstr())
103 switch (SU->getInstr()->getOpcode()) {
105 if (!ResourcesModel->canReserveResources(*SU->getInstr()))
119 MachineBasicBlock *MBB = SU->getInstr()->getParent();
127 if (hasDependence(Packet[i], SU, QII))
131 if (hasDependence(SU, Packet[i], QII))
138 bool VLIWResourceModel::reserveResources(SUnit *SU, bool IsTop)
[all...] |
| /src/libexec/getty/ |
| gettytab.h | 83 #define SU gettystrs[18].value
|
| /src/games/battlestar/ |
| extern.h | 148 #define SU 1014
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| trinityd.h | 202 # define SU(x) ((x) << 16)
|
| sumod.h | 209 # define SU(x) ((x) << 23)
|
