1 /* $NetBSD: sunxi_gpio.c,v 1.39 2024/08/13 07:20:23 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_soc.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sunxi_gpio.c,v 1.39 2024/08/13 07:20:23 skrll Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/mutex.h> 40 #include <sys/kmem.h> 41 #include <sys/gpio.h> 42 #include <sys/bitops.h> 43 #include <sys/lwp.h> 44 45 #include <dev/fdt/fdtvar.h> 46 #include <dev/gpio/gpiovar.h> 47 48 #include <arm/sunxi/sunxi_gpio.h> 49 50 #define SUNXI_GPIO_MAX_EINT_BANK 5 51 #define SUNXI_GPIO_MAX_EINT 32 52 53 #define SUNXI_GPIO_MAX_BANK 26 54 55 #define SUNXI_GPIO_PORT(port) (0x24 * (port)) 56 #define SUNXI_GPIO_CFG(port, pin) (SUNXI_GPIO_PORT(port) + 0x00 + (0x4 * ((pin) / 8))) 57 #define SUNXI_GPIO_CFG_PINMASK(pin) (0x7U << (((pin) % 8) * 4)) 58 #define SUNXI_GPIO_DATA(port) (SUNXI_GPIO_PORT(port) + 0x10) 59 #define SUNXI_GPIO_DRV(port, pin) (SUNXI_GPIO_PORT(port) + 0x14 + (0x4 * ((pin) / 16))) 60 #define SUNXI_GPIO_DRV_PINMASK(pin) (0x3U << (((pin) % 16) * 2)) 61 #define SUNXI_GPIO_PULL(port, pin) (SUNXI_GPIO_PORT(port) + 0x1c + (0x4 * ((pin) / 16))) 62 #define SUNXI_GPIO_PULL_DISABLE 0 63 #define SUNXI_GPIO_PULL_UP 1 64 #define SUNXI_GPIO_PULL_DOWN 2 65 #define SUNXI_GPIO_PULL_PINMASK(pin) (0x3U << (((pin) % 16) * 2)) 66 #define SUNXI_GPIO_INT_CFG(bank, eint) (0x200 + (0x20 * (bank)) + (0x4 * ((eint) / 8))) 67 #define SUNXI_GPIO_INT_MODEMASK(eint) (0xfU << (((eint) % 8) * 4)) 68 #define SUNXI_GPIO_INT_MODE_POS_EDGE 0x0 69 #define SUNXI_GPIO_INT_MODE_NEG_EDGE 0x1 70 #define SUNXI_GPIO_INT_MODE_HIGH_LEVEL 0x2 71 #define SUNXI_GPIO_INT_MODE_LOW_LEVEL 0x3 72 #define SUNXI_GPIO_INT_MODE_DOUBLE_EDGE 0x4 73 #define SUNXI_GPIO_INT_CTL(bank) (0x210 + 0x20 * (bank)) 74 #define SUNXI_GPIO_INT_STATUS(bank) (0x214 + 0x20 * (bank)) 75 #define SUNXI_GPIO_INT_DEBOUNCE(bank) (0x218 + 0x20 * (bank)) 76 #define SUNXI_GPIO_INT_DEBOUNCE_CLK_PRESCALE __BITS(6,4) 77 #define SUNXI_GPIO_INT_DEBOUNCE_CLK_SEL __BIT(0) 78 #define SUNXI_GPIO_GRP_CONFIG(bank) (0x300 + 0x4 * (bank)) 79 #define SUNXI_GPIO_GRP_IO_BIAS_CONFIGMASK 0xf 80 81 static const struct device_compatible_entry compat_data[] = { 82 #ifdef SOC_SUN4I_A10 83 { .compat = "allwinner,sun4i-a10-pinctrl", 84 .data = &sun4i_a10_padconf }, 85 #endif 86 #ifdef SOC_SUN5I_A13 87 { .compat = "allwinner,sun5i-a13-pinctrl", 88 .data = &sun5i_a13_padconf }, 89 { .compat = "nextthing,gr8-pinctrl", 90 .data = &sun5i_a13_padconf }, 91 #endif 92 #ifdef SOC_SUN6I_A31 93 { .compat = "allwinner,sun6i-a31-pinctrl", 94 .data = &sun6i_a31_padconf }, 95 { .compat = "allwinner,sun6i-a31-r-pinctrl", 96 .data = &sun6i_a31_r_padconf }, 97 #endif 98 #ifdef SOC_SUN7I_A20 99 { .compat = "allwinner,sun7i-a20-pinctrl", 100 .data = &sun7i_a20_padconf }, 101 #endif 102 #ifdef SOC_SUN8I_A83T 103 { .compat = "allwinner,sun8i-a83t-pinctrl", 104 .data = &sun8i_a83t_padconf }, 105 { .compat = "allwinner,sun8i-a83t-r-pinctrl", 106 .data = &sun8i_a83t_r_padconf }, 107 #endif 108 #ifdef SOC_SUN8I_H3 109 { .compat = "allwinner,sun8i-h3-pinctrl", 110 .data = &sun8i_h3_padconf }, 111 { .compat = "allwinner,sun8i-h3-r-pinctrl", 112 .data = &sun8i_h3_r_padconf }, 113 #endif 114 #ifdef SOC_SUN8I_V3S 115 { .compat = "allwinner,sun8i-v3s-pinctrl", 116 .data = &sun8i_v3s_padconf }, 117 #endif 118 #ifdef SOC_SUN9I_A80 119 { .compat = "allwinner,sun9i-a80-pinctrl", 120 .data = &sun9i_a80_padconf }, 121 { .compat = "allwinner,sun9i-a80-r-pinctrl", 122 .data = &sun9i_a80_r_padconf }, 123 #endif 124 #ifdef SOC_SUN20I_D1 125 { .compat = "allwinner,sun20i-d1-pinctrl", 126 .data = &sun20i_d1_padconf }, 127 #endif 128 #ifdef SOC_SUN50I_A64 129 { .compat = "allwinner,sun50i-a64-pinctrl", 130 .data = &sun50i_a64_padconf }, 131 { .compat = "allwinner,sun50i-a64-r-pinctrl", 132 .data = &sun50i_a64_r_padconf }, 133 #endif 134 #ifdef SOC_SUN50I_H5 135 { .compat = "allwinner,sun50i-h5-pinctrl", 136 .data = &sun8i_h3_padconf }, 137 { .compat = "allwinner,sun50i-h5-r-pinctrl", 138 .data = &sun8i_h3_r_padconf }, 139 #endif 140 #ifdef SOC_SUN50I_H6 141 { .compat = "allwinner,sun50i-h6-pinctrl", 142 .data = &sun50i_h6_padconf }, 143 { .compat = "allwinner,sun50i-h6-r-pinctrl", 144 .data = &sun50i_h6_r_padconf }, 145 #endif 146 DEVICE_COMPAT_EOL 147 }; 148 149 struct sunxi_gpio_eint { 150 int (*eint_func)(void *); 151 void *eint_arg; 152 bool eint_mpsafe; 153 int eint_bank; 154 int eint_num; 155 }; 156 157 struct sunxi_gpio_softc { 158 device_t sc_dev; 159 bus_space_tag_t sc_bst; 160 bus_space_handle_t sc_bsh; 161 int sc_phandle; 162 const struct sunxi_gpio_padconf *sc_padconf; 163 kmutex_t sc_lock; 164 165 struct gpio_chipset_tag sc_gp; 166 gpio_pin_t *sc_pins; 167 device_t sc_gpiodev; 168 169 struct fdtbus_regulator *sc_pin_supply[SUNXI_GPIO_MAX_BANK]; 170 171 u_int sc_eint_bank_max; 172 173 void *sc_ih; 174 struct sunxi_gpio_eint sc_eint[SUNXI_GPIO_MAX_EINT_BANK][SUNXI_GPIO_MAX_EINT]; 175 }; 176 177 struct sunxi_gpio_pin { 178 struct sunxi_gpio_softc *pin_sc; 179 const struct sunxi_gpio_pins *pin_def; 180 int pin_flags; 181 bool pin_actlo; 182 }; 183 184 #define GPIO_READ(sc, reg) \ 185 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 186 #define GPIO_WRITE(sc, reg, val) \ 187 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 188 189 static int sunxi_gpio_match(device_t, cfdata_t, void *); 190 static void sunxi_gpio_attach(device_t, device_t, void *); 191 192 CFATTACH_DECL_NEW(sunxi_gpio, sizeof(struct sunxi_gpio_softc), 193 sunxi_gpio_match, sunxi_gpio_attach, NULL, NULL); 194 195 static const struct sunxi_gpio_pins * 196 sunxi_gpio_lookup(struct sunxi_gpio_softc *sc, uint8_t port, uint8_t pin) 197 { 198 const struct sunxi_gpio_pins *pin_def; 199 u_int n; 200 201 for (n = 0; n < sc->sc_padconf->npins; n++) { 202 pin_def = &sc->sc_padconf->pins[n]; 203 if (pin_def->port == port && pin_def->pin == pin) 204 return pin_def; 205 } 206 207 return NULL; 208 } 209 210 static const struct sunxi_gpio_pins * 211 sunxi_gpio_lookup_byname(struct sunxi_gpio_softc *sc, const char *name) 212 { 213 const struct sunxi_gpio_pins *pin_def; 214 u_int n; 215 216 for (n = 0; n < sc->sc_padconf->npins; n++) { 217 pin_def = &sc->sc_padconf->pins[n]; 218 if (strcmp(pin_def->name, name) == 0) 219 return pin_def; 220 } 221 222 return NULL; 223 } 224 225 static int 226 sunxi_gpio_setfunc(struct sunxi_gpio_softc *sc, 227 const struct sunxi_gpio_pins *pin_def, const char *func) 228 { 229 uint32_t cfg; 230 u_int n; 231 232 KASSERT(mutex_owned(&sc->sc_lock)); 233 234 const bus_size_t cfg_reg = SUNXI_GPIO_CFG(pin_def->port, pin_def->pin); 235 const uint32_t cfg_mask = SUNXI_GPIO_CFG_PINMASK(pin_def->pin); 236 237 for (n = 0; n < SUNXI_GPIO_MAXFUNC; n++) { 238 if (pin_def->functions[n] == NULL) 239 continue; 240 if (strcmp(pin_def->functions[n], func) == 0) { 241 cfg = GPIO_READ(sc, cfg_reg); 242 cfg &= ~cfg_mask; 243 cfg |= __SHIFTIN(n, cfg_mask); 244 #ifdef SUNXI_GPIO_DEBUG 245 device_printf(sc->sc_dev, "P%c%02d cfg %08x -> %08x\n", 246 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, cfg_reg), cfg); 247 #endif 248 GPIO_WRITE(sc, cfg_reg, cfg); 249 return 0; 250 } 251 } 252 253 /* Function not found */ 254 device_printf(sc->sc_dev, "function '%s' not supported on P%c%02d\n", 255 func, pin_def->port + 'A', pin_def->pin); 256 257 return ENXIO; 258 } 259 260 static int 261 sunxi_gpio_setpull(struct sunxi_gpio_softc *sc, 262 const struct sunxi_gpio_pins *pin_def, int flags) 263 { 264 uint32_t pull; 265 266 KASSERT(mutex_owned(&sc->sc_lock)); 267 268 const bus_size_t pull_reg = SUNXI_GPIO_PULL(pin_def->port, pin_def->pin); 269 const uint32_t pull_mask = SUNXI_GPIO_PULL_PINMASK(pin_def->pin); 270 271 pull = GPIO_READ(sc, pull_reg); 272 pull &= ~pull_mask; 273 if (flags & GPIO_PIN_PULLUP) 274 pull |= __SHIFTIN(SUNXI_GPIO_PULL_UP, pull_mask); 275 else if (flags & GPIO_PIN_PULLDOWN) 276 pull |= __SHIFTIN(SUNXI_GPIO_PULL_DOWN, pull_mask); 277 else 278 pull |= __SHIFTIN(SUNXI_GPIO_PULL_DISABLE, pull_mask); 279 #ifdef SUNXI_GPIO_DEBUG 280 device_printf(sc->sc_dev, "P%c%02d pull %08x -> %08x\n", 281 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, pull_reg), pull); 282 #endif 283 GPIO_WRITE(sc, pull_reg, pull); 284 285 return 0; 286 } 287 288 static int 289 sunxi_gpio_setdrv(struct sunxi_gpio_softc *sc, 290 const struct sunxi_gpio_pins *pin_def, int drive_strength) 291 { 292 uint32_t drv; 293 294 KASSERT(mutex_owned(&sc->sc_lock)); 295 296 if (drive_strength < 10 || drive_strength > 40) 297 return EINVAL; 298 299 const bus_size_t drv_reg = SUNXI_GPIO_DRV(pin_def->port, pin_def->pin); 300 const uint32_t drv_mask = SUNXI_GPIO_DRV_PINMASK(pin_def->pin); 301 302 drv = GPIO_READ(sc, drv_reg); 303 drv &= ~drv_mask; 304 drv |= __SHIFTIN((drive_strength / 10) - 1, drv_mask); 305 #ifdef SUNXI_GPIO_DEBUG 306 device_printf(sc->sc_dev, "P%c%02d drv %08x -> %08x\n", 307 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, drv_reg), drv); 308 #endif 309 GPIO_WRITE(sc, drv_reg, drv); 310 311 return 0; 312 } 313 314 static int 315 sunxi_gpio_ctl(struct sunxi_gpio_softc *sc, const struct sunxi_gpio_pins *pin_def, 316 int flags) 317 { 318 KASSERT(mutex_owned(&sc->sc_lock)); 319 320 if (flags & GPIO_PIN_INPUT) 321 return sunxi_gpio_setfunc(sc, pin_def, "gpio_in"); 322 if (flags & GPIO_PIN_OUTPUT) 323 return sunxi_gpio_setfunc(sc, pin_def, "gpio_out"); 324 325 return EINVAL; 326 } 327 328 static void * 329 sunxi_gpio_acquire(device_t dev, const void *data, size_t len, int flags) 330 { 331 struct sunxi_gpio_softc * const sc = device_private(dev); 332 const struct sunxi_gpio_pins *pin_def; 333 struct sunxi_gpio_pin *gpin; 334 const u_int *gpio = data; 335 int error; 336 337 if (len != 16) 338 return NULL; 339 340 const uint8_t port = be32toh(gpio[1]) & 0xff; 341 const uint8_t pin = be32toh(gpio[2]) & 0xff; 342 const bool actlo = be32toh(gpio[3]) & 1; 343 344 pin_def = sunxi_gpio_lookup(sc, port, pin); 345 if (pin_def == NULL) 346 return NULL; 347 348 mutex_enter(&sc->sc_lock); 349 error = sunxi_gpio_ctl(sc, pin_def, flags); 350 mutex_exit(&sc->sc_lock); 351 352 if (error != 0) 353 return NULL; 354 355 gpin = kmem_zalloc(sizeof(*gpin), KM_SLEEP); 356 gpin->pin_sc = sc; 357 gpin->pin_def = pin_def; 358 gpin->pin_flags = flags; 359 gpin->pin_actlo = actlo; 360 361 return gpin; 362 } 363 364 static void 365 sunxi_gpio_release(device_t dev, void *priv) 366 { 367 struct sunxi_gpio_softc * const sc = device_private(dev); 368 struct sunxi_gpio_pin *pin = priv; 369 370 mutex_enter(&sc->sc_lock); 371 sunxi_gpio_ctl(pin->pin_sc, pin->pin_def, GPIO_PIN_INPUT); 372 mutex_exit(&sc->sc_lock); 373 374 kmem_free(pin, sizeof(*pin)); 375 } 376 377 static int 378 sunxi_gpio_read(device_t dev, void *priv, bool raw) 379 { 380 struct sunxi_gpio_softc * const sc = device_private(dev); 381 struct sunxi_gpio_pin *pin = priv; 382 const struct sunxi_gpio_pins *pin_def = pin->pin_def; 383 uint32_t data; 384 int val; 385 386 KASSERT(sc == pin->pin_sc); 387 388 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 389 const uint32_t data_mask = __BIT(pin_def->pin); 390 391 /* No lock required for reads */ 392 data = GPIO_READ(sc, data_reg); 393 val = __SHIFTOUT(data, data_mask); 394 if (!raw && pin->pin_actlo) 395 val = !val; 396 397 #ifdef SUNXI_GPIO_DEBUG 398 device_printf(dev, "P%c%02d rd %08x (%d %d)\n", 399 pin_def->port + 'A', pin_def->pin, data, 400 __SHIFTOUT(val, data_mask), val); 401 #endif 402 403 return val; 404 } 405 406 static void 407 sunxi_gpio_write(device_t dev, void *priv, int val, bool raw) 408 { 409 struct sunxi_gpio_softc * const sc = device_private(dev); 410 struct sunxi_gpio_pin *pin = priv; 411 const struct sunxi_gpio_pins *pin_def = pin->pin_def; 412 uint32_t data; 413 414 KASSERT(sc == pin->pin_sc); 415 416 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 417 const uint32_t data_mask = __BIT(pin_def->pin); 418 419 if (!raw && pin->pin_actlo) 420 val = !val; 421 422 mutex_enter(&sc->sc_lock); 423 data = GPIO_READ(sc, data_reg); 424 data &= ~data_mask; 425 data |= __SHIFTIN(val, data_mask); 426 #ifdef SUNXI_GPIO_DEBUG 427 device_printf(dev, "P%c%02d wr %08x -> %08x\n", 428 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, data_reg), data); 429 #endif 430 GPIO_WRITE(sc, data_reg, data); 431 mutex_exit(&sc->sc_lock); 432 } 433 434 static struct fdtbus_gpio_controller_func sunxi_gpio_funcs = { 435 .acquire = sunxi_gpio_acquire, 436 .release = sunxi_gpio_release, 437 .read = sunxi_gpio_read, 438 .write = sunxi_gpio_write, 439 }; 440 441 static int 442 sunxi_gpio_intr(void *priv) 443 { 444 struct sunxi_gpio_softc * const sc = priv; 445 struct sunxi_gpio_eint *eint; 446 uint32_t status, bit; 447 u_int bank; 448 int ret = 0; 449 450 for (bank = 0; bank <= sc->sc_eint_bank_max; bank++) { 451 status = GPIO_READ(sc, SUNXI_GPIO_INT_STATUS(bank)); 452 if (status == 0) 453 continue; 454 GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS(bank), status); 455 456 while ((bit = ffs32(status)) != 0) { 457 status &= ~__BIT(bit - 1); 458 eint = &sc->sc_eint[bank][bit - 1]; 459 if (eint->eint_func == NULL) 460 continue; 461 if (!eint->eint_mpsafe) 462 KERNEL_LOCK(1, curlwp); 463 ret |= eint->eint_func(eint->eint_arg); 464 if (!eint->eint_mpsafe) 465 KERNEL_UNLOCK_ONE(curlwp); 466 } 467 } 468 469 return ret; 470 } 471 472 static void * 473 sunxi_intr_enable(struct sunxi_gpio_softc *sc, 474 const struct sunxi_gpio_pins *pin_def, u_int mode, bool mpsafe, 475 int (*func)(void *), void *arg) 476 { 477 uint32_t val; 478 struct sunxi_gpio_eint *eint; 479 480 if (pin_def->functions[pin_def->eint_func] == NULL || 481 strcmp(pin_def->functions[pin_def->eint_func], "irq") != 0) 482 return NULL; 483 484 KASSERT(pin_def->eint_num < SUNXI_GPIO_MAX_EINT); 485 486 mutex_enter(&sc->sc_lock); 487 488 eint = &sc->sc_eint[pin_def->eint_bank][pin_def->eint_num]; 489 if (eint->eint_func != NULL) { 490 mutex_exit(&sc->sc_lock); 491 return NULL; /* in use */ 492 } 493 494 /* Set function */ 495 if (sunxi_gpio_setfunc(sc, pin_def, "irq") != 0) { 496 mutex_exit(&sc->sc_lock); 497 return NULL; 498 } 499 500 eint->eint_func = func; 501 eint->eint_arg = arg; 502 eint->eint_mpsafe = mpsafe; 503 eint->eint_bank = pin_def->eint_bank; 504 eint->eint_num = pin_def->eint_num; 505 506 /* Configure eint mode */ 507 val = GPIO_READ(sc, SUNXI_GPIO_INT_CFG(eint->eint_bank, eint->eint_num)); 508 val &= ~SUNXI_GPIO_INT_MODEMASK(eint->eint_num); 509 val |= __SHIFTIN(mode, SUNXI_GPIO_INT_MODEMASK(eint->eint_num)); 510 GPIO_WRITE(sc, SUNXI_GPIO_INT_CFG(eint->eint_bank, eint->eint_num), val); 511 512 val = SUNXI_GPIO_INT_DEBOUNCE_CLK_SEL; 513 GPIO_WRITE(sc, SUNXI_GPIO_INT_DEBOUNCE(eint->eint_bank), val); 514 515 /* Enable eint */ 516 val = GPIO_READ(sc, SUNXI_GPIO_INT_CTL(eint->eint_bank)); 517 val |= __BIT(eint->eint_num); 518 GPIO_WRITE(sc, SUNXI_GPIO_INT_CTL(eint->eint_bank), val); 519 520 mutex_exit(&sc->sc_lock); 521 522 return eint; 523 } 524 525 static void 526 sunxi_intr_disable(struct sunxi_gpio_softc *sc, struct sunxi_gpio_eint *eint) 527 { 528 uint32_t val; 529 530 KASSERT(eint->eint_func != NULL); 531 532 mutex_enter(&sc->sc_lock); 533 534 /* Disable eint */ 535 val = GPIO_READ(sc, SUNXI_GPIO_INT_CTL(eint->eint_bank)); 536 val &= ~__BIT(eint->eint_num); 537 GPIO_WRITE(sc, SUNXI_GPIO_INT_CTL(eint->eint_bank), val); 538 GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS(eint->eint_bank), __BIT(eint->eint_num)); 539 540 eint->eint_func = NULL; 541 eint->eint_arg = NULL; 542 eint->eint_mpsafe = false; 543 544 mutex_exit(&sc->sc_lock); 545 } 546 547 static void * 548 sunxi_fdt_intr_establish(device_t dev, u_int *specifier, int ipl, int flags, 549 int (*func)(void *), void *arg, const char *xname) 550 { 551 struct sunxi_gpio_softc * const sc = device_private(dev); 552 bool mpsafe = (flags & FDT_INTR_MPSAFE) != 0; 553 const struct sunxi_gpio_pins *pin_def; 554 u_int mode; 555 556 if (ipl != IPL_VM) { 557 aprint_error_dev(dev, "%s: wrong IPL %d (expected %d)\n", 558 __func__, ipl, IPL_VM); 559 return NULL; 560 } 561 562 /* 1st cell is the bank */ 563 /* 2nd cell is the pin */ 564 /* 3rd cell is flags */ 565 const u_int port = be32toh(specifier[0]); 566 const u_int pin = be32toh(specifier[1]); 567 const u_int type = be32toh(specifier[2]) & 0xf; 568 569 switch (type) { 570 case FDT_INTR_TYPE_POS_EDGE: 571 mode = SUNXI_GPIO_INT_MODE_POS_EDGE; 572 break; 573 case FDT_INTR_TYPE_NEG_EDGE: 574 mode = SUNXI_GPIO_INT_MODE_NEG_EDGE; 575 break; 576 case FDT_INTR_TYPE_DOUBLE_EDGE: 577 mode = SUNXI_GPIO_INT_MODE_DOUBLE_EDGE; 578 break; 579 case FDT_INTR_TYPE_HIGH_LEVEL: 580 mode = SUNXI_GPIO_INT_MODE_HIGH_LEVEL; 581 break; 582 case FDT_INTR_TYPE_LOW_LEVEL: 583 mode = SUNXI_GPIO_INT_MODE_LOW_LEVEL; 584 break; 585 default: 586 aprint_error_dev(dev, "%s: unsupported irq type 0x%x\n", 587 __func__, type); 588 return NULL; 589 } 590 591 pin_def = sunxi_gpio_lookup(sc, port, pin); 592 if (pin_def == NULL) 593 return NULL; 594 595 return sunxi_intr_enable(sc, pin_def, mode, mpsafe, func, arg); 596 } 597 598 static void 599 sunxi_fdt_intr_disestablish(device_t dev, void *ih) 600 { 601 struct sunxi_gpio_softc * const sc = device_private(dev); 602 struct sunxi_gpio_eint * const eint = ih; 603 604 sunxi_intr_disable(sc, eint); 605 } 606 607 static bool 608 sunxi_fdt_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 609 { 610 struct sunxi_gpio_softc * const sc = device_private(dev); 611 const struct sunxi_gpio_pins *pin_def; 612 613 /* 1st cell is the bank */ 614 /* 2nd cell is the pin */ 615 /* 3rd cell is flags */ 616 if (!specifier) 617 return false; 618 const u_int port = be32toh(specifier[0]); 619 const u_int pin = be32toh(specifier[1]); 620 621 pin_def = sunxi_gpio_lookup(sc, port, pin); 622 if (pin_def == NULL) 623 return false; 624 625 snprintf(buf, buflen, "GPIO %s", pin_def->name); 626 627 return true; 628 } 629 630 static struct fdtbus_interrupt_controller_func sunxi_gpio_intrfuncs = { 631 .establish = sunxi_fdt_intr_establish, 632 .disestablish = sunxi_fdt_intr_disestablish, 633 .intrstr = sunxi_fdt_intrstr, 634 }; 635 636 static void * 637 sunxi_gpio_intr_establish(void *vsc, int pin, int ipl, int irqmode, 638 int (*func)(void *), void *arg) 639 { 640 struct sunxi_gpio_softc * const sc = vsc; 641 bool mpsafe = (irqmode & GPIO_INTR_MPSAFE) != 0; 642 int type = irqmode & GPIO_INTR_MODE_MASK; 643 const struct sunxi_gpio_pins *pin_def; 644 u_int mode; 645 646 switch (type) { 647 case GPIO_INTR_POS_EDGE: 648 mode = SUNXI_GPIO_INT_MODE_POS_EDGE; 649 break; 650 case GPIO_INTR_NEG_EDGE: 651 mode = SUNXI_GPIO_INT_MODE_NEG_EDGE; 652 break; 653 case GPIO_INTR_DOUBLE_EDGE: 654 mode = SUNXI_GPIO_INT_MODE_DOUBLE_EDGE; 655 break; 656 case GPIO_INTR_HIGH_LEVEL: 657 mode = SUNXI_GPIO_INT_MODE_HIGH_LEVEL; 658 break; 659 case GPIO_INTR_LOW_LEVEL: 660 mode = SUNXI_GPIO_INT_MODE_LOW_LEVEL; 661 break; 662 default: 663 aprint_error_dev(sc->sc_dev, "%s: unsupported irq type 0x%x\n", 664 __func__, type); 665 return NULL; 666 } 667 668 if (pin < 0 || pin >= sc->sc_padconf->npins) 669 return NULL; 670 pin_def = &sc->sc_padconf->pins[pin]; 671 672 return sunxi_intr_enable(sc, pin_def, mode, mpsafe, func, arg); 673 } 674 675 static void 676 sunxi_gpio_intr_disestablish(void *vsc, void *ih) 677 { 678 struct sunxi_gpio_softc * const sc = vsc; 679 struct sunxi_gpio_eint * const eint = ih; 680 681 sunxi_intr_disable(sc, eint); 682 } 683 684 static bool 685 sunxi_gpio_intrstr(void *vsc, int pin, int irqmode, char *buf, size_t buflen) 686 { 687 struct sunxi_gpio_softc * const sc = vsc; 688 const struct sunxi_gpio_pins *pin_def; 689 690 if (pin < 0 || pin >= sc->sc_padconf->npins) 691 return NULL; 692 pin_def = &sc->sc_padconf->pins[pin]; 693 694 snprintf(buf, buflen, "GPIO %s", pin_def->name); 695 696 return true; 697 } 698 699 static const char * 700 sunxi_pinctrl_parse_function(int phandle) 701 { 702 const char *function; 703 704 function = fdtbus_pinctrl_parse_function(phandle); 705 if (function != NULL) 706 return function; 707 708 return fdtbus_get_string(phandle, "allwinner,function"); 709 } 710 711 static const char * 712 sunxi_pinctrl_parse_pins(int phandle, int *pins_len) 713 { 714 const char *pins; 715 int len; 716 717 pins = fdtbus_pinctrl_parse_pins(phandle, pins_len); 718 if (pins != NULL) 719 return pins; 720 721 len = OF_getproplen(phandle, "allwinner,pins"); 722 if (len > 0) { 723 *pins_len = len; 724 return fdtbus_get_prop(phandle, "allwinner,pins", pins_len); 725 } 726 727 return NULL; 728 } 729 730 static int 731 sunxi_pinctrl_parse_bias(int phandle) 732 { 733 u_int pull; 734 int bias; 735 736 bias = fdtbus_pinctrl_parse_bias(phandle, NULL); 737 if (bias != -1) 738 return bias; 739 740 if (of_getprop_uint32(phandle, "allwinner,pull", &pull) == 0) { 741 switch (pull) { 742 case 0: 743 bias = 0; 744 break; 745 case 1: 746 bias = GPIO_PIN_PULLUP; 747 break; 748 case 2: 749 bias = GPIO_PIN_PULLDOWN; 750 break; 751 } 752 } 753 754 return bias; 755 } 756 757 static int 758 sunxi_pinctrl_parse_drive_strength(int phandle) 759 { 760 int val; 761 762 val = fdtbus_pinctrl_parse_drive_strength(phandle); 763 if (val != -1) 764 return val; 765 766 if (of_getprop_uint32(phandle, "allwinner,drive", &val) == 0) 767 return (val + 1) * 10; 768 769 return -1; 770 } 771 772 static void 773 sunxi_pinctrl_enable_regulator(struct sunxi_gpio_softc *sc, 774 const struct sunxi_gpio_pins *pin_def) 775 { 776 char supply_prop[16]; 777 uint32_t val; 778 u_int uvol; 779 int error; 780 781 const char c = tolower(pin_def->name[1]); 782 if (c < 'a' || c > 'z') 783 return; 784 const int index = c - 'a'; 785 786 if (sc->sc_pin_supply[index] != NULL) { 787 /* Already enabled */ 788 return; 789 } 790 791 snprintf(supply_prop, sizeof(supply_prop), "vcc-p%c-supply", c); 792 sc->sc_pin_supply[index] = fdtbus_regulator_acquire(sc->sc_phandle, supply_prop); 793 if (sc->sc_pin_supply[index] == NULL) 794 return; 795 796 aprint_debug_dev(sc->sc_dev, "enable \"%s\"\n", supply_prop); 797 error = fdtbus_regulator_enable(sc->sc_pin_supply[index]); 798 if (error != 0) 799 aprint_error_dev(sc->sc_dev, "failed to enable %s: %d\n", supply_prop, error); 800 801 if (sc->sc_padconf->has_io_bias_config) { 802 error = fdtbus_regulator_get_voltage(sc->sc_pin_supply[index], &uvol); 803 if (error != 0) { 804 aprint_error_dev(sc->sc_dev, "failed to get %s voltage: %d\n", 805 supply_prop, error); 806 uvol = 0; 807 } 808 if (uvol != 0) { 809 if (uvol <= 1800000) 810 val = 0x0; /* 1.8V */ 811 else if (uvol <= 2500000) 812 val = 0x6; /* 2.5V */ 813 else if (uvol <= 2800000) 814 val = 0x9; /* 2.8V */ 815 else if (uvol <= 3000000) 816 val = 0xa; /* 3.0V */ 817 else 818 val = 0xd; /* 3.3V */ 819 820 aprint_debug_dev(sc->sc_dev, "set io bias config for port %d to 0x%x\n", 821 pin_def->port, val); 822 val = GPIO_READ(sc, SUNXI_GPIO_GRP_CONFIG(pin_def->port)); 823 val &= ~SUNXI_GPIO_GRP_IO_BIAS_CONFIGMASK; 824 val |= __SHIFTIN(val, SUNXI_GPIO_GRP_IO_BIAS_CONFIGMASK); 825 GPIO_WRITE(sc, SUNXI_GPIO_GRP_CONFIG(pin_def->port), val); 826 } 827 } 828 } 829 830 static int 831 sunxi_pinctrl_set_config(device_t dev, const void *data, size_t len) 832 { 833 struct sunxi_gpio_softc * const sc = device_private(dev); 834 const struct sunxi_gpio_pins *pin_def; 835 int pins_len; 836 837 if (len != 4) 838 return -1; 839 840 const int phandle = fdtbus_get_phandle_from_native(be32dec(data)); 841 842 /* 843 * Required: pins, function 844 * Optional: bias, drive strength 845 */ 846 847 const char *function = sunxi_pinctrl_parse_function(phandle); 848 if (function == NULL) 849 return -1; 850 const char *pins = sunxi_pinctrl_parse_pins(phandle, &pins_len); 851 if (pins == NULL) 852 return -1; 853 854 const int bias = sunxi_pinctrl_parse_bias(phandle); 855 const int drive_strength = sunxi_pinctrl_parse_drive_strength(phandle); 856 857 mutex_enter(&sc->sc_lock); 858 859 for (; pins_len > 0; 860 pins_len -= strlen(pins) + 1, pins += strlen(pins) + 1) { 861 pin_def = sunxi_gpio_lookup_byname(sc, pins); 862 if (pin_def == NULL) { 863 aprint_error_dev(dev, "unknown pin name '%s'\n", pins); 864 continue; 865 } 866 if (sunxi_gpio_setfunc(sc, pin_def, function) != 0) 867 continue; 868 869 if (bias != -1) 870 sunxi_gpio_setpull(sc, pin_def, bias); 871 872 if (drive_strength != -1) 873 sunxi_gpio_setdrv(sc, pin_def, drive_strength); 874 875 sunxi_pinctrl_enable_regulator(sc, pin_def); 876 } 877 878 mutex_exit(&sc->sc_lock); 879 880 return 0; 881 } 882 883 static struct fdtbus_pinctrl_controller_func sunxi_pinctrl_funcs = { 884 .set_config = sunxi_pinctrl_set_config, 885 }; 886 887 static int 888 sunxi_gpio_pin_read(void *priv, int pin) 889 { 890 struct sunxi_gpio_softc * const sc = priv; 891 const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[pin]; 892 uint32_t data; 893 int val; 894 895 KASSERT(pin < sc->sc_padconf->npins); 896 897 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 898 const uint32_t data_mask = __BIT(pin_def->pin); 899 900 /* No lock required for reads */ 901 data = GPIO_READ(sc, data_reg); 902 val = __SHIFTOUT(data, data_mask); 903 904 return val; 905 } 906 907 static void 908 sunxi_gpio_pin_write(void *priv, int pin, int val) 909 { 910 struct sunxi_gpio_softc * const sc = priv; 911 const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[pin]; 912 uint32_t data; 913 914 KASSERT(pin < sc->sc_padconf->npins); 915 916 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 917 const uint32_t data_mask = __BIT(pin_def->pin); 918 919 mutex_enter(&sc->sc_lock); 920 data = GPIO_READ(sc, data_reg); 921 if (val) 922 data |= data_mask; 923 else 924 data &= ~data_mask; 925 GPIO_WRITE(sc, data_reg, data); 926 mutex_exit(&sc->sc_lock); 927 } 928 929 static void 930 sunxi_gpio_pin_ctl(void *priv, int pin, int flags) 931 { 932 struct sunxi_gpio_softc * const sc = priv; 933 const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[pin]; 934 935 KASSERT(pin < sc->sc_padconf->npins); 936 937 mutex_enter(&sc->sc_lock); 938 sunxi_gpio_ctl(sc, pin_def, flags); 939 sunxi_gpio_setpull(sc, pin_def, flags); 940 mutex_exit(&sc->sc_lock); 941 } 942 943 static void 944 sunxi_gpio_attach_ports(struct sunxi_gpio_softc *sc) 945 { 946 const struct sunxi_gpio_pins *pin_def; 947 struct gpio_chipset_tag *gp = &sc->sc_gp; 948 struct gpiobus_attach_args gba; 949 u_int pin; 950 951 gp->gp_cookie = sc; 952 gp->gp_pin_read = sunxi_gpio_pin_read; 953 gp->gp_pin_write = sunxi_gpio_pin_write; 954 gp->gp_pin_ctl = sunxi_gpio_pin_ctl; 955 gp->gp_intr_establish = sunxi_gpio_intr_establish; 956 gp->gp_intr_disestablish = sunxi_gpio_intr_disestablish; 957 gp->gp_intr_str = sunxi_gpio_intrstr; 958 959 const u_int npins = sc->sc_padconf->npins; 960 sc->sc_pins = kmem_zalloc(sizeof(*sc->sc_pins) * npins, KM_SLEEP); 961 962 for (pin = 0; pin < sc->sc_padconf->npins; pin++) { 963 pin_def = &sc->sc_padconf->pins[pin]; 964 sc->sc_pins[pin].pin_num = pin; 965 sc->sc_pins[pin].pin_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | 966 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN; 967 if (pin_def->functions[pin_def->eint_func] != NULL && 968 strcmp(pin_def->functions[pin_def->eint_func], "irq") == 0) { 969 sc->sc_pins[pin].pin_intrcaps = 970 GPIO_INTR_POS_EDGE | GPIO_INTR_NEG_EDGE | 971 GPIO_INTR_HIGH_LEVEL | GPIO_INTR_LOW_LEVEL | 972 GPIO_INTR_DOUBLE_EDGE | GPIO_INTR_MPSAFE; 973 } 974 sc->sc_pins[pin].pin_state = sunxi_gpio_pin_read(sc, pin); 975 strlcpy(sc->sc_pins[pin].pin_defname, pin_def->name, 976 sizeof(sc->sc_pins[pin].pin_defname)); 977 } 978 979 memset(&gba, 0, sizeof(gba)); 980 gba.gba_gc = gp; 981 gba.gba_pins = sc->sc_pins; 982 gba.gba_npins = npins; 983 sc->sc_gpiodev = config_found(sc->sc_dev, &gba, NULL, CFARGS_NONE); 984 } 985 986 static int 987 sunxi_gpio_match(device_t parent, cfdata_t cf, void *aux) 988 { 989 struct fdt_attach_args * const faa = aux; 990 991 return of_compatible_match(faa->faa_phandle, compat_data); 992 } 993 994 static void 995 sunxi_gpio_attach(device_t parent, device_t self, void *aux) 996 { 997 struct sunxi_gpio_softc * const sc = device_private(self); 998 struct fdt_attach_args * const faa = aux; 999 const int phandle = faa->faa_phandle; 1000 char intrstr[128]; 1001 struct fdtbus_reset *rst; 1002 struct clk *clk; 1003 bus_addr_t addr; 1004 bus_size_t size; 1005 int child; 1006 1007 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 1008 aprint_error(": couldn't get registers\n"); 1009 return; 1010 } 1011 1012 if ((clk = fdtbus_clock_get_index(phandle, 0)) != NULL) 1013 if (clk_enable(clk) != 0) { 1014 aprint_error(": couldn't enable clock\n"); 1015 return; 1016 } 1017 1018 if ((rst = fdtbus_reset_get_index(phandle, 0)) != NULL) 1019 if (fdtbus_reset_deassert(rst) != 0) { 1020 aprint_error(": couldn't de-assert reset\n"); 1021 return; 1022 } 1023 1024 sc->sc_dev = self; 1025 sc->sc_phandle = phandle; 1026 sc->sc_bst = faa->faa_bst; 1027 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 1028 aprint_error(": couldn't map registers\n"); 1029 return; 1030 } 1031 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 1032 sc->sc_padconf = of_compatible_lookup(phandle, compat_data)->data; 1033 1034 aprint_naive("\n"); 1035 aprint_normal(": PIO\n"); 1036 1037 fdtbus_register_gpio_controller(self, phandle, &sunxi_gpio_funcs); 1038 1039 for (child = OF_child(phandle); child; child = OF_peer(child)) { 1040 bool is_valid = 1041 (of_hasprop(child, "function") && of_hasprop(child, "pins")) || 1042 (of_hasprop(child, "allwinner,function") && of_hasprop(child, "allwinner,pins")); 1043 if (!is_valid) 1044 continue; 1045 fdtbus_register_pinctrl_config(self, child, &sunxi_pinctrl_funcs); 1046 } 1047 1048 sunxi_gpio_attach_ports(sc); 1049 1050 /* Disable all external interrupts */ 1051 for (int i = 0; i < sc->sc_padconf->npins; i++) { 1052 const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[i]; 1053 if (pin_def->eint_func == 0) 1054 continue; 1055 GPIO_WRITE(sc, SUNXI_GPIO_INT_CTL(pin_def->eint_bank), __BIT(pin_def->eint_num)); 1056 GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS(pin_def->eint_bank), __BIT(pin_def->eint_num)); 1057 1058 if (sc->sc_eint_bank_max < pin_def->eint_bank) 1059 sc->sc_eint_bank_max = pin_def->eint_bank; 1060 } 1061 KASSERT(sc->sc_eint_bank_max < SUNXI_GPIO_MAX_EINT_BANK); 1062 1063 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 1064 aprint_error_dev(self, "failed to decode interrupt\n"); 1065 return; 1066 } 1067 sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_VM, 1068 FDT_INTR_MPSAFE, sunxi_gpio_intr, sc, device_xname(self)); 1069 if (sc->sc_ih == NULL) { 1070 aprint_error_dev(self, "failed to establish interrupt on %s\n", 1071 intrstr); 1072 return; 1073 } 1074 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 1075 fdtbus_register_interrupt_controller(self, phandle, 1076 &sunxi_gpio_intrfuncs); 1077 } 1078
Indexes created Fri Sep 26 20:09:58 GMT 2025