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    Searched defs:SVT (Results 1 - 14 of 14) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeDAG.cpp 306 EVT SVT = VT;
311 while (SVT != MVT::f32 && SVT != MVT::f16) {
312 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
313 if (ConstantFPSDNode::isValueValidForType(SVT, APF) &&
316 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) &&
318 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
320 VT = SVT;
3203 MVT SVT = Op.getSimpleValueType()
    [all...]
LegalizeFloatTypes.cpp 751 EVT SVT = N->getOperand(IsStrict ? 1 : 0).getValueType();
764 if (NVT.bitsGE(SVT))
775 CallOptions.setTypeListBeforeSoften(SVT, RVT, true);
870 EVT SVT = Op.getValueType();
874 RTLIB::Libcall LC = RTLIB::getFPROUND(SVT, FloatRVT);
880 CallOptions.setTypeListBeforeSoften(SVT, RVT, true);
940 EVT SVT = Op.getValueType();
949 RTLIB::Libcall LC = findFPToIntLibcall(SVT, RVT, NVT, Signed);
956 CallOptions.setTypeListBeforeSoften(SVT, RVT, true);
LegalizeIntegerTypes.cpp 288 EVT SVT = getSetCCResultType(N->getOperand(2).getValueType());
293 if (!TLI.isTypeLegal(SVT))
294 SVT = NVT;
296 SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other);
575 EVT SVT = In.getValueType().getScalarType();
576 if (SVT.bitsGE(NVT)) {
577 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, In, Op1);
741 EVT SVT = getSetCCResultType(VT);
749 SDValue Res = DAG.getNode(N->getOpcode(), dl, DAG.getVTList(VT, SVT),
1065 EVT SVT = getSetCCResultType(InVT)
    [all...]
LegalizeVectorTypes.cpp 5005 EVT SVT = getSetCCResultType(InOp0.getValueType());
5008 SVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
5009 SVT.getVectorNumElements());
5012 SVT, InOp0, InOp1, N->getOperand(2));
5016 SVT.getVectorElementType(),
TargetLowering.cpp 5019 EVT SVT = VT.getScalarType();
5041 Factors.push_back(DAG.getConstant(Factor, dl, SVT));
5098 EVT SVT = VT.getScalarType();
5151 MagicFactors.push_back(DAG.getConstant(magics.m, dl, SVT));
5152 Factors.push_back(DAG.getConstant(NumeratorFactor, dl, SVT));
5154 ShiftMasks.push_back(DAG.getConstant(ShiftMask, dl, SVT));
5246 EVT SVT = VT.getScalarType();
5305 MagicFactors.push_back(DAG.getConstant(Magic, dl, SVT));
5309 dl, SVT));
5469 EVT SVT = VT.getScalarType()
    [all...]
DAGCombiner.cpp 2510 EVT SVT = N0.getOperand(0).getValueType();
2511 SDValue NewStep = DAG.getConstant(C0 + C1, DL, SVT);
2521 EVT SVT = N1.getOperand(0).getValueType();
2525 SDValue NewStep = DAG.getConstant(SV0 + SV1, DL, SVT);
3933 EVT SVT = N0.getOperand(0).getValueType();
3935 C0 * MulVal.sextOrTrunc(SVT.getSizeInBits()), SDLoc(N), SVT);
8432 EVT SVT = N0.getOperand(0).getValueType();
8434 C0 << ShlVal.sextOrTrunc(SVT.getSizeInBits()), SDLoc(N), SVT);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetLoweringBase.cpp 933 MVT SVT = VT.getSimpleVT();
934 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
935 MVT NVT = TransformToType[SVT.SimpleTy];
936 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
945 return LegalizeKind(LA, EVT(SVT).getHalfNumVectorElementsVT(Context));
947 return LegalizeKind(LA, SVT.getVectorElementType());
1383 MVT SVT = (MVT::SimpleValueType) nVT;
1386 if (SVT.getScalarSizeInBits() > EltVT.getFixedSizeInBits() &&
1387 SVT.getVectorElementCount() == EC && isTypeLegal(SVT)) {
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsSEISelLowering.cpp 426 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
438 switch (SVT) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstCombineIntrinsic.cpp 203 auto SVT = VT->getElementType();
206 unsigned BitWidth = SVT->getPrimitiveSizeInBits();
216 Amt = Builder.CreateZExtOrTrunc(Amt, SVT);
225 Amt = ConstantInt::get(SVT, BitWidth - 1);
232 cast<VectorType>(AmtVT)->getElementType() == SVT &&
259 cast<VectorType>(AmtVT)->getElementType() == SVT &&
286 auto ShiftAmt = ConstantInt::get(SVT, Count.zextOrTrunc(BitWidth));
351 auto SVT = VT->getElementType();
353 int BitWidth = SVT->getIntegerBitWidth();
406 ConstantVec.push_back(UndefValue::get(SVT));
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelDAGToDAG.cpp 1210 EVT SVT = (UW == 32 || UW == 64) ? MVT::getIntegerVT(UW) : UVT;
1211 SDValue Sel = DAG.getNode(ISD::SELECT, dl, SVT, OpI1,
1212 DAG.getBitcast(SVT, If1),
1213 DAG.getBitcast(SVT, If0));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIISelLowering.cpp 11066 MVT SVT = Node->getValueType(0).getVectorElementType().getSimpleVT();
11069 SVT : MVT::getVectorVT(SVT, NewChannels == 3 ? 4 :
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 1721 MVT SVT = VT.getVectorElementType();
1739 Offset *= SVT.getStoreSize();
1744 if (SVT.isInteger() && SVT.bitsGT(XLenVT)) {
1751 ISD::INTRINSIC_W_CHAIN, DL, VTs, Ops, SVT,
1753 Ld->getMemOperand(), Offset, SVT.getStoreSize()));
1761 if (SVT.isFloatingPoint())
1762 V = DAG.getLoad(SVT, DL, Ld->getChain(), NewAddr,
1768 Ld->getPointerInfo().getWithOffset(Offset), SVT,
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 6739 static const TargetRegisterClass *getRegClassForSVT(MVT::SimpleValueType SVT,
6741 assert((IsPPC64 || SVT != MVT::i64) &&
6744 switch (SVT) {
6929 MVT::SimpleValueType SVT = VA.getLocVT().SimpleTy;
6930 MF.addLiveIn(VA.getLocReg(), getRegClassForSVT(SVT, IsPPC64));
7040 MVT::SimpleValueType SVT = ValVT.SimpleTy;
7042 MF.addLiveIn(VA.getLocReg(), getRegClassForSVT(SVT, IsPPC64));
10886 EVT SVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
10888 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 8318 EVT SVT = VT.getScalarType() == MVT::i8 || VT.getScalarType() == MVT::i16
8322 ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18675 const SDNode *N, MVT::SimpleValueType SVT) {
18682 switch (SVT) {

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