HomeSort by: relevance | last modified time | path
    Searched defs:ScalarSize (Results 1 - 7 of 7) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64PostLegalizerLowering.cpp 663 unsigned ScalarSize = ScalarTy.getSizeInBits();
668 if (ScalarSize == 64)
670 else if (ScalarSize == 32)
674 if (ScalarSize == 32)
678 if (ScalarSize == 16)
682 if (ScalarSize == 8)
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InterleavedAccess.cpp 234 unsigned ScalarSize = VT.getVectorElementType().getScalarSizeInBits() * 2;
235 return MVT::getVectorVT(MVT::getIntegerVT(ScalarSize),
X86TargetTransformInfo.cpp 3701 unsigned ScalarSize = ValVTy->getScalarSizeInBits();
3705 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits())
3726 unsigned Size = NumVecElts * ScalarSize;
4021 unsigned ScalarSize = ValTy->getScalarSizeInBits();
4026 ScalarSize != MTy.getScalarSizeInBits())
4034 unsigned Size = NumVecElts * ScalarSize;
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/
VectorCombine.cpp 139 uint64_t ScalarSize = ScalarTy->getPrimitiveSizeInBits();
141 if (!ScalarSize || !MinVectorSize || MinVectorSize % ScalarSize != 0 ||
142 ScalarSize % 8 != 0)
149 unsigned MinVecNumElts = MinVectorSize / ScalarSize;
169 uint64_t ScalarSizeInBytes = ScalarSize / 8;
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelDAGToDAG.cpp 168 unsigned ScalarSize = VT.getScalarSizeInBits();
181 addVectorLoadStoreOperands(Node, ScalarSize, DL, CurOp, IsMasked, IsStrided,
185 RISCV::getVLSEGPseudo(NF, IsMasked, IsStrided, /*FF*/ false, ScalarSize,
209 unsigned ScalarSize = VT.getScalarSizeInBits();
222 addVectorLoadStoreOperands(Node, ScalarSize, DL, CurOp, IsMasked,
227 ScalarSize, static_cast<unsigned>(LMUL));
253 unsigned ScalarSize = VT.getScalarSizeInBits();
267 addVectorLoadStoreOperands(Node, ScalarSize, DL, CurOp, IsMasked,
304 unsigned ScalarSize = VT.getScalarSizeInBits();
313 addVectorLoadStoreOperands(Node, ScalarSize, DL, CurOp, IsMasked, IsStrided
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUCodeGenPrepare.cpp 151 unsigned numBitsUnsigned(Value *Op, unsigned ScalarSize) const;
152 unsigned numBitsSigned(Value *Op, unsigned ScalarSize) const;
153 bool isI24(Value *V, unsigned ScalarSize) const;
154 bool isU24(Value *V, unsigned ScalarSize) const;
443 unsigned ScalarSize) const {
445 return ScalarSize - Known.countMinLeadingZeros();
449 unsigned ScalarSize) const {
452 return ScalarSize - ComputeNumSignBits(Op, *DL, 0, AC);
455 bool AMDGPUCodeGenPrepare::isI24(Value *V, unsigned ScalarSize) const {
456 return ScalarSize >= 24 && // Types less than 24-bit should be treate
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 17952 unsigned ScalarSize = Op.getScalarValueSizeInBits();
17953 assert(ScalarSize > ShiftLBits && "Invalid shift imm");
17955 APInt ZeroBits = APInt::getLowBitsSet(ScalarSize, ShiftLBits);

Completed in 38 milliseconds