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    Searched defs:ScaledReg (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
ImplicitNullChecks.cpp 380 const Register BaseReg = AddrMode.BaseReg, ScaledReg = AddrMode.ScaledReg;
385 if (BaseReg != PointerReg && ScaledReg != PointerReg)
389 // Bail out of the sizes of BaseReg, ScaledReg and PointerReg are not the
393 (ScaledReg &&
394 TRI->getRegSizeInBits(ScaledReg, MRI) != PointerRegSizeInBits))
403 // ScaledReg is %rdi, while there is no BaseReg.
453 if (CalculateDisplacementFromAddrMode(ScaledReg, AddrMode.Scale))
462 (ScaledReg && ScaledReg != PointerReg && !ScaledRegIsConstVal)
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CodeGenPrepare.cpp 232 cl::desc("Allow combining of ScaledReg field in Address sinking."));
2426 Value *ScaledReg = nullptr;
2455 if (ScaledReg && other.ScaledReg &&
2456 ScaledReg->getType() != other.ScaledReg->getType())
2471 if (ScaledReg != other.ScaledReg)
2474 // unscaled (which will already be counted by having no ScaledReg).
2503 return ScaledReg;
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  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
TargetInstrInfo.h 88 Register ScaledReg;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIRegisterInfo.cpp 1750 Register ScaledReg = ResultReg;
1753 ScaledReg)
1763 MIB.addReg(ScaledReg, RegState::Kill);
1780 MIB.addReg(ScaledReg, RegState::Kill);
1792 Register ScaledReg = TmpScaledReg.isValid() ? TmpScaledReg : FrameReg;
1794 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_LSHR_B32), ScaledReg)
1797 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), ScaledReg)
1798 .addReg(ScaledReg, RegState::Kill)
1801 .addReg(ScaledReg, RegState::Kill);
1805 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_SUB_U32), ScaledReg)
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  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
LoopStrengthReduce.cpp 159 // the same ScaledReg and Scale.
163 " with the same ScaledReg and Scale"));
354 /// 1. BaseRegs.size > 1 implies ScaledReg != NULL and
355 /// 2. ScaledReg != NULL implies Scale != 1 || !BaseRegs.empty().
357 /// formula should be put in the ScaledReg.
370 const SCEV *ScaledReg = nullptr;
482 if (!ScaledReg)
491 const SCEVAddRecExpr *SAR = dyn_cast<const SCEVAddRecExpr>(ScaledReg);
495 // If ScaledReg is not a recurrent expr, or it is but its loop is not current
497 // loop, we want to swap the reg in BaseRegs with ScaledReg
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