| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| ARCISelDAGToDAG.cpp | 35 /// ARCDAGToDAGISel - ARC specific code to select ARC machine
44 void Select(SDNode *N) override;
169 void ARCDAGToDAGISel::Select(SDNode *N) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiISelDAGToDAG.cpp | 43 // LanaiDAGToDAGISel - Lanai specific code to select Lanai machine
70 void Select(SDNode *N) override;
270 // Select instructions not customized! Used for
272 void LanaiDAGToDAGISel::Select(SDNode *Node) {
311 // Select the default instruction
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEISelDAGToDAG.cpp | 117 /// VEDAGToDAGISel - VE specific code to select VE machine
134 void Select(SDNode *N) override;
330 void VEDAGToDAGISel::Select(SDNode *N) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelDAGToDAG.cpp | 30 /// WebAssembly-specific code to select WebAssembly machine instructions for
59 void Select(SDNode *Node) override;
68 // add select functions here...
72 void WebAssemblyDAGToDAGISel::Select(SDNode *Node) {
194 // Select the default instruction.
|
| WebAssemblyFastISel.cpp | 909 const auto *Select = cast<SelectInst>(I);
912 unsigned CondReg = getRegForI1Value(Select->getCondition(), Not);
916 unsigned TrueReg = getRegForValue(Select->getTrueValue());
920 unsigned FalseReg = getRegForValue(Select->getFalseValue());
929 switch (getSimpleType(Select->getType())) {
967 updateValueMap(Select, ResultReg);
1398 case Instruction::Select:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | 75 /// Select - Select instructions not customized! Used for
77 void NVPTXDAGToDAGISel::Select(SDNode *N) {
490 // Try to select BFE
1668 // In this case, the matching logic above will select a load for the original
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreISelDAGToDAG.cpp | 34 /// XCoreDAGToDAGISel - XCore specific code to select XCore machine
44 void Select(SDNode *N) override;
132 void XCoreDAGToDAGISel::Select(SDNode *N) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 88 /// MSP430DAGToDAGISel - MSP430 specific code to select MSP430 machine
113 void Select(SDNode *N) override;
170 // If so, we cannot select it.
377 void MSP430DAGToDAGISel::Select(SDNode *Node) {
458 // Select the default instruction
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsISelDAGToDAG.cpp | 45 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
265 /// Select instructions not customized! Used for
267 void MipsDAGToDAGISel::Select(SDNode *Node) {
306 // Select the default instruction
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 27 /// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
43 void Select(SDNode *N) override;
322 void SparcDAGToDAGISel::Select(SDNode *N) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRISelDAGToDAG.cpp | 50 void Select(SDNode *N) override;
53 template <unsigned NodeType> bool select(SDNode *N);
305 template <> bool AVRDAGToDAGISel::select<ISD::FrameIndex>(SDNode *N) { function in class:llvm::AVRDAGToDAGISel
320 template <> bool AVRDAGToDAGISel::select<ISD::STORE>(SDNode *N) { function in class:llvm::AVRDAGToDAGISel
357 template <> bool AVRDAGToDAGISel::select<ISD::LOAD>(SDNode *N) { function in class:llvm::AVRDAGToDAGISel
413 template <> bool AVRDAGToDAGISel::select<AVRISD::CALL>(SDNode *N) { function in class:llvm::AVRDAGToDAGISel
453 template <> bool AVRDAGToDAGISel::select<ISD::BRIND>(SDNode *N) { function in class:llvm::AVRDAGToDAGISel
513 void AVRDAGToDAGISel::Select(SDNode *N) {
525 // Select the default instruction
535 case ISD::FrameIndex: return select<ISD::FrameIndex>(N)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFISelDAGToDAG.cpp | 71 void Select(SDNode *N) override;
180 void BPFDAGToDAGISel::Select(SDNode *Node) {
240 // Select the default instruction
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kISelDAGToDAG.cpp | 199 void Select(SDNode *N) override;
379 // Otherwise, we cannot select it.
616 void M68kDAGToDAGISel::Select(SDNode *Node) {
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| MCInstrDesc.h | 162 Select,
341 /// Return true if this is a select instruction.
342 bool isSelect() const { return Flags & (1ULL << MCID::Select); }
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelDAGToDAG.cpp | 365 void RISCVDAGToDAGISel::Select(SDNode *Node) {
436 // By default we do not custom select any intrinsic.
443 // Only custom select scalar second operand.
512 // Only custom select scalar second operand.
618 // By default we do not custom select any intrinsic.
1180 // Select the default instruction.
1211 // If this is FrameIndex, select it directly. Otherwise just let it get
1325 // Select VL as a 5 bit immediate or a value that will become a register. This
|
| /src/external/apache2/llvm/dist/clang/lib/CodeGen/ |
| CGExprAgg.cpp | 1047 Value *Select;
1049 Select = EmitCmpRes(CmpInfo.getEqualOrEquiv());
1054 Select = Builder.CreateSelect(EmitCmp(CK_Equal),
1064 Select = Builder.CreateSelect(
1075 CGF.EmitStoreThroughLValue(RValue::get(Select), FieldLV, /*IsInit*/ true);
|
| /src/external/apache2/llvm/dist/clang/utils/TableGen/ |
| ClangDiagnosticsEmitter.cpp | 454 return "select";
727 CASE(Select);
914 // Render %diff{a $ b $ c|d}e,f as %select{a %e b %f c|d}.
925 SelectPiece Select(MT_Diff);
926 Select.Options.push_back(&FirstOption);
927 Select.Options.push_back(P->Parts[3]);
929 VisitSelect(&Select);
1047 .Case("select", MT_Select)
1069 SelectPiece *Select = New<SelectPiece>(MT_Select);
1072 Select->Options.push_back
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 371 void Select(SDNode *Node) override;
1019 // Now, select the machine opcode to implement this operation.
1342 // Before we try to select anything, make sure this is memory operand size
1507 void SystemZDAGToDAGISel::Select(SDNode *Node) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/ |
| InstCombineAddSub.cpp | 968 // TODO: The smallest IR representation is (select X, 0, 1), and that would
970 // visitSelect and make sure that IR value tracking for select is equal or
1158 // right-shift of X and a "select".
1159 Value *X, *Select;
1164 m_Value(Select))))
1167 // `add`/`or` is commutative; but for `sub`, "select" *must* be on RHS.
1168 if (I.getOpcode() == Instruction::Sub && I.getOperand(1) != Select)
1203 // `select` itself may be appropriately extended, look past that.
1204 SkipExtInMagic(Select);
1210 // It must be a select between two values we will later establish to be
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/ |
| LoopUtils.cpp | 943 Value *Select = Builder.CreateSelect(Cmp, Left, Right, "rdx.minmax.select");
944 return Select;
|
| /src/external/apache2/llvm/dist/llvm/lib/IR/ |
| AutoUpgrade.cpp | 1536 Value* Select = Builder.CreateSelect(Cmp, Extract1, Extract2);
1537 return Builder.CreateInsertElement(A, Select, (uint64_t)0);
1549 // Replace intrinsic with unmasked version and a select.
2439 // If there are 3 arguments, it's a masked intrinsic so we need a select.
2683 // [1:0] - select 128 bits from sources for low half of destination
2686 // [5:4] - select 128 bits from sources for high half of destination
2794 // Now select the specific element. By adding HalfLaneElts bits from
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 33 /// AArch64DAGToDAGISel - AArch64 specific code to select AArch64 machine
58 void Select(SDNode *Node) override;
392 /// SelectArithImmed - Select an immediate value that can be represented as
424 /// select it.
521 /// SelectShiftedRegister - Select a "shifted register" operand. If the value
638 /// is a lane in the upper half of a 128-bit vector. Recognize and select this
763 /// SelectArithExtendedRegister - Select a "extended register" operand. This
829 /// SelectAddrModeIndexedBitWidth - Select a "register plus scaled (un)signed BW-bit
892 /// SelectAddrModeIndexed - Select a "register plus scaled unsigned 12-bit
950 /// SelectAddrModeUnscaled - Select a "register plus unscaled signed 9-bi
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelDAGToDAG.cpp | 98 /// AMDGPU specific code to select AMDGPU machine instructions for
132 void Select(SDNode *N) override;
296 void Select(SDNode *N) override;
702 void AMDGPUDAGToDAGISel::Select(SDNode *N) {
1237 // FIXME: Select to VOP3 version for with-carry.
2284 // For the case that we select S_CBRANCH_SCC1 and it gets
2332 // TODO: We can select this with f32 denormals enabled if all the sources are
2800 // Really a scalar input. Just select from the low half of the register to
3067 void R600DAGToDAGISel::Select(SDNode *N) {
|
| AMDGPUInstructionSelector.cpp | 34 "amdgpu-global-isel-risky-select",
35 cl::desc("Allow GlobalISel to select cases that are likely to not work yet"),
1784 MachineInstr *Select = BuildMI(*BB, &I, DL, TII.get(SelectOpcode), DstReg)
1788 bool Ret = constrainSelectedInstRegOperands(*Select, TII, TRI, RBI) |
1794 // Wide VGPR select should have been split in RegBankSelect.
1798 MachineInstr *Select =
1806 bool Ret = constrainSelectedInstRegOperands(*Select, TII, TRI, RBI);
3052 bool AMDGPUInstructionSelector::select(MachineInstr &I) { function in class:AMDGPUInstructionSelector
3226 /// This will select either an SGPR or VGPR operand and will save us from
3420 // then we can select all ptr + 32-bit offsets not just immediate offsets
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 883 void HexagonDAGToDAGISel::Select(SDNode *N) {
982 // Transform: (or (select c x 0) z) -> (select c (or x z) z)
983 // (or (select c 0 y) z) -> (select c z (or y z))
997 if (Op.getOpcode() != ISD::SELECT)
1008 if (SOp.getOpcode() == ISD::SELECT && SOp.getNode()->hasOneUse()) {
1015 SDValue NewSel = DAG.getNode(ISD::SELECT, DLS, VT, SC, NewOr, VOp);
1019 SDValue NewSel = DAG.getNode(ISD::SELECT, DLS, VT, SC, VOp, NewOr);
1159 // Transform: (op ... (zext i1 c) ...) -> (select c (op ... 0 ...
[all...] |
